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LaTeX output does not get generated #2
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From what I found out so far, there is a problem in
|
Jan, Thanks for all the documentation. A couple quick ideas: Have you tried putting the doxygen comment for the signal after the signal name? Such as:
Does the same behavior occur if you have two signals? I have found that certain items act odd when acting upon or involving the last item in a port list (in VHDL at least). For example if you have a group:
Sorry, I know that example is in VHDL, but that's what I happen to be writing in at the moment...the same idea should apply to Verilog though, since they use pretty much the same parsing elements. |
Unfortunately neither moving the doxygen comment after the signal name neither adding more signals does not resolve this issue. I did however managed to generate LaTeX output by forcing
Does it have any sense to have |
There is a bug which halts generation of LaTeX output when the project is composed of multiple Verilog modules.
Follows a minimal example which enables replication of this bug. When the line
input clk
insimple_submodule.v
is commented out, the LaTeX output is correctly generated and this is the contents of thelatex
directory:When the line
input clk
is present therefman.tex
is missing:Files
top_module.v
simple_submodule.v
verilog.cfg (Doxverilog configuration file)
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