diff --git a/docs/directives/hdl-diagram.rst b/docs/directives/hdl-diagram.rst
index 4add46f..0507a76 100644
--- a/docs/directives/hdl-diagram.rst
+++ b/docs/directives/hdl-diagram.rst
@@ -12,7 +12,7 @@ The `hdl-diagram` RST directive can be used to generate a diagram from HDL code
 
 .. note::
 
-   The `verilog-diagram` directive is kept as an alias of this directive for 
+   The `verilog-diagram` directive is kept as an alias of this directive for
    compatibility purposes.
 
 Options
@@ -117,8 +117,9 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/dff.v
-   :type: yosys-bb
+..
+  .. hdl-diagram:: ../code/verilog/dff.v
+     :type: yosys-bb
 
 
 Yosys AIG Diagram
@@ -137,8 +138,9 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/dff.v
-   :type: yosys-aig
+..
+  .. hdl-diagram:: ../code/verilog/dff.v
+     :type: yosys-aig
 
 
 NetlistSVG Diagram
diff --git a/docs/examples/comb-full-adder.rst b/docs/examples/comb-full-adder.rst
index d97f764..3ba2323 100644
--- a/docs/examples/comb-full-adder.rst
+++ b/docs/examples/comb-full-adder.rst
@@ -40,9 +40,10 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/adder.v
-   :type: yosys-bb
-   :module: ADDER
+..
+  .. hdl-diagram:: ../code/verilog/adder.v
+     :type: yosys-bb
+     :module: ADDER
 
 
 Yosys AIG Diagram
@@ -62,9 +63,10 @@ RST Directive
 Result
 ******
 
-.. hdl-diagram:: ../code/verilog/adder.v
-   :type: yosys-aig
-   :module: ADDER
+..
+  .. hdl-diagram:: ../code/verilog/adder.v
+     :type: yosys-aig
+     :module: ADDER
 
 
 NetlistSVG Diagram