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I was able to improve the clock tree of my design dramatically by increasing max routing layer from default M7 in ASAP7 to M9 for a design that has macros and where it routing the clock tree on top of the macros reduces latency and skew for the clock tree. However, this is not an explicit instruction to the CTS algorithm, it is more freedom for CTS to create lower latency and skew.
Q: Are there any explicit ways or other less explicit ways to control how the clock tree is generated? |
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The CTS command has a lot of knobs but they are most useful with an autotuner. I suspect you had more of a problem with routing detouring than cts itself. |
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The CTS command has a lot of knobs but they are most useful with an autotuner. I suspect you had more of a problem with routing detouring than cts itself.