Unexpected failures of OpenROAD flow #1675
Replies: 6 comments 21 replies
-
What is ASYNC_DFFHx1_ASAP7_75t_R? it is in your .v but not in the asap7 platorm. |
Beta Was this translation helpful? Give feedback.
-
I see this is in the older _27 rev of asap7 and was removed in _28. I'll pull it from there. There isn't any simple answer to make everything work. We'll have to look at the issues one by one and see what they are. |
Beta Was this translation helpful? Give feedback.
-
I started with the hang reported in floorplan at the lower-left. I can't reproduce it as the design goes through without delay for me. Please package a test case using 'make floorplan_issue' so that it is complete. |
Beta Was this translation helpful? Give feedback.
-
Would you give the ORFS version you are using? (git rev-parse HEAD). I see your OR version is from the end of Sept. |
Beta Was this translation helpful? Give feedback.
-
While waiting on 3200,2048 could you package a test for 400,51 ? |
Beta Was this translation helpful? Give feedback.
-
The hang at 3200,2048 is resolved by The-OpenROAD-Project/OpenROAD#4358. I haven't run the full flow but floorplan finishes. |
Beta Was this translation helpful? Give feedback.
-
Recently, I have been trying to synthesize circuits through OpenROAD (with asap7 library), but some of those runs either failed or hung depending on the core area and clock period constraints (utilization was kept constant at 80%). My example runs for a netlist with 10^4 instances are shown in the table below. I have also attached the input Verilog netlist, and an example of the config.mk and constraint.sdc files I used.
Can you please explain the following observations, as shown in the table below?
(a) For area 2048, reducing clock period from 3200 to 400 results in completion.
(b) Flow completes with area 52 and clock period 400, but hangs when area reduced to 51. However, completes again with area 51 only at a lower clock period 100.
Can you please help me understand what is going on, and suggest guidelines for reliable configuration for OpenROAD flow to complete?
Thanks,
Ishwar S.
verilog netlist: tc3_1e4.v.zip
config.mk: config.mk.zip
constraint.sdc: constraint.sdc.zip
The table below says "HANG @ <some step>" to indicate that OpenROAD hangs indefinitely after printing the line "<some step> report_checks -path_delay max" for the given core area and clock period.
Beta Was this translation helpful? Give feedback.
All reactions