Unconstrained paths

[naveen17440]

Hello all,
I am new to this OpenROAD flow.

I am exploring the OpenROAD tools with sky130hd riscv32i design. In this design I have 3 unconstrained endpoints at floorplan stage

The default constrained file : OpenROAD-flow-scripts/flow/designs/sky130hd/riscv32i/constraint.sdc

I have modified the sdc file with these 3 constraints:
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [get_ports reset]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [get_ports instr]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [get_ports readdata]

After using the above constraints, I'm not seen any unconstrained paths in the log, but timing is violated.

I tried to explore unconstrained paths that are reported in log file and found it is a TIE HIGH/TIE LOW cells.

I've asked some expert , they said not to constrain tie high or low cells in constraint file.

For small design it is easy trace path and can be ignored those warning reported in the log file.

For complex design it is difficult to trace all the paths that are connected to TIE HIGH/LOW.

Is there any feature in the tool to suppress that message, like those nets are connected to TIE HIGH/LOW constants, so it will be easy to trace and constraint remaining path alone.

Thanks...

[maliberty]

There are no timing paths through a TIE cell. If you are seeing such it is a bug but that's unlikely. Your description is rather garbled but I am guessing you mean you want to assume a signal is constant that isn't tied off. In that case you would use the set_case_analysis command in your SDC. set_logic_one/set_logic_zero are similar but the constant isn't propagated.

[rovinski]

If it is constant but of unknown value, you can use set_false_path.

[naveen17440]

set non_clock_inputs [list]
foreach input [all_inputs] {
    if {$clk_port != $input} {
        lappend $non_clock_inputs $input
    }
}

After updating above lines to below format ,

set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

I am not seeing any unconstrained paths in the logs now.

Thanks for your information.