Clockgate demo

flow/platforms/asap7/config.mk

@@ -80,6 +80,7 @@ export DONT_USE_CELLS          += SDF* ICG*
 # Yosys mapping files
 export LATCH_MAP_FILE          = $(PLATFORM_DIR)/yoSys/cells_latch_R.v
 export CLKGATE_MAP_FILE        = $(PLATFORM_DIR)/yoSys/cells_clkgate_R.v
+export CLOCKGATE_CMD = clockgate -pos ICGx1_ASAP7_75t_R ENA:CLK:GCLK -min_net_size 8 -tie_lo SE
 export ADDER_MAP_FILE         ?= $(PLATFORM_DIR)/yoSys/cells_adders_R.v
 export MAX_UNGROUP_SIZE       ?= 100
 
@@ -176,6 +177,7 @@ ifeq ($(ASAP7_USELVT), 1)
 
    export LATCH_MAP_FILE          = $(PLATFORM_DIR)/yoSys/cells_latch_L.v
    export CLKGATE_MAP_FILE        = $(PLATFORM_DIR)/yoSys/cells_clkgate_L.v
+   export CLOCKGATE_CMD = clockgate -pos ICGx1_ASAP7_75t_L ENA:CLK:GCLK -min_net_size 8 -tie_lo SE
    export ADDER_MAP_FILE         ?= $(PLATFORM_DIR)/yoSys/cells_adders_L.v
 
    export BC_NLDM_DFF_LIB_FILE         = $(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
@@ -225,6 +227,7 @@ ifeq ($(ASAP7_USESLVT), 1)
 
    export LATCH_MAP_FILE          = $(PLATFORM_DIR)/yoSys/cells_latch_SL.v
    export CLKGATE_MAP_FILE        = $(PLATFORM_DIR)/yoSys/cells_clkgate_SL.v
+   export CLOCKGATE_CMD = clockgate -pos ICGx1_ASAP7_75t_SL ENA:CLK:GCLK -min_net_size 8 -tie_lo SE
    export ADDER_MAP_FILE         ?= $(PLATFORM_DIR)/yoSys/cells_adders_SL.v
 
    export BC_NLDM_DFF_LIB_FILE        = $(LIB_DIR)/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib

flow/platforms/ihp-sg13g2/config.mk

@@ -56,6 +56,9 @@ export ABC_DRIVER_CELL = sg13g2_buf_4
 export ABC_LOAD_IN_FF = 6.0
 # Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file
 export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}')
+
+export CLOCKGATE_CMD = clockgate -pos sg13g2_lgcp_1 GATE:CLK:GCLK -min_net_size 8
+
 #--------------------------------------------------------
 # Floorplan
 # -------------------------------------------------------

flow/platforms/nangate45/config.mk

@@ -41,6 +41,8 @@ export ABC_DRIVER_CELL = BUF_X1
 # BUF_X1, pin (A) = 0.974659. Arbitrarily multiply by 4
 export ABC_LOAD_IN_FF = 3.898
 
+export CLOCKGATE_CMD = clockgate -pos CLKGATE_X1 E:CK:GCK -min_net_size 8
+
 #--------------------------------------------------------
 # Floorplan
 # -------------------------------------------------------

flow/platforms/sky130hd/config.mk

@@ -77,6 +77,9 @@ export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hd.v
 # Define ABC driver and load
 export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
 export ABC_LOAD_IN_FF = 5
+
+export CLOCKGATE_CMD = clockgate -pos sky130_fd_sc_hd__dlclkp_4 GATE:CLK:GCLK -min_net_size 8
+
 #--------------------------------------------------------
 # Floorplan
 # -------------------------------------------------------

flow/platforms/sky130hs/config.mk

@@ -39,6 +39,8 @@ export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/cells_adders_hs.v
 # Define ABC driver and load
 export ABC_DRIVER_CELL = sky130_fd_sc_hs__buf_1
 export ABC_LOAD_IN_FF = 5
+export CLOCKGATE_CMD = clockgate -pos sky130_fd_sc_hs__dlclkp_4 GATE:CLK:GCLK -min_net_size 8
+
 #--------------------------------------------------------
 # Floorplan
 # -------------------------------------------------------

flow/scripts/synth.tcl

@@ -40,6 +40,10 @@ foreach cell $::env(DONT_USE_CELLS) {
   lappend dfflibmap_args -dont_use $cell
 }
 
+if {[env_var_exists_and_non_empty CLOCKGATE_CMD]} {
+  yosys $::env(CLOCKGATE_CMD)
+}
+
 # Technology mapping of flip-flops
 # dfflibmap only supports one liberty file
 if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {