Observations w.r.t. timing closure for MegaBoom using floorplan timing information

[oharboe]

Since the turnaround times are long(12 hours at least), actionable information must be teased out as early as possible.

Here I'm trying to understand a bit of what is going on by looking at timing information from the floorplan stage.

I already know there is a problem with synchronous reset. It should have multiple pipeline stages to handle the enormous fanout, but I can't find that anywhere in the Verilog.

Here is another case of very large fan-outs. I don't know what is going on, but I suspect that this is another case of retiming and register duplication in synthesis is assumed in the articulation of the RTL.