getting more detailed timing reports for macros by loading .v instead of .lib file

[oharboe]

I naively hoped to see if I could get more detailed timing numbers on mock-array Elements when loading the .v file instead of .lib file, but when I load .v files for macros instead of .lib files, I don't get any timing information.

Perhaps this is obviously futile, but it would be nice to understand why...

make DESIGN_CONFIG=designs/asap7/mock-array/config.mk gui_cts

With changes below:

>>> report_checks -from {ces_3_1/io_lsbOuts_7} -to {ces_3_5/io_lsbIns_4}
No paths found.

Without:

>>> report_checks -from {ces_3_1/io_lsbOuts_7} -to {ces_3_5/io_lsbIns_4}
  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 317.39  317.39   clock network delay (propagated)
   0.00  317.39 ^ ces_3_1/clock (Element)
 161.13  478.52 ^ ces_3_1/io_lsbOuts_7 (Element)
  39.99  518.51 ^ ces_3_2/io_lsbOuts_6 (Element)
  37.50  556.01 ^ ces_3_3/io_lsbOuts_5 (Element)
  32.82  588.84 ^ ces_3_4/io_lsbOuts_4 (Element)
   0.00  588.84 ^ ces_3_5/io_lsbIns_4 (Element)
         588.84   data arrival time

 250.00  250.00   clock clock (rise edge)
 272.57  522.57   clock network delay (propagated)
   7.60  530.17   clock reconvergence pessimism
         530.17 ^ ces_3_5/clock (Element)
  49.03  579.20   library setup time
         579.20   data required time
---------------------------------------------------------
         579.20   data required time
        -588.84   data arrival time
---------------------------------------------------------
          -9.64   slack (VIOLATED)

diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl
index 75938163..bff9fe26 100644
--- a/flow/scripts/generate_abstract.tcl
+++ b/flow/scripts/generate_abstract.tcl
@@ -25,6 +25,10 @@ puts "Generating abstract views"
 write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib
 write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef
 
+# OpenSTA does not read .lib/.lef files
+write_verilog $::env(RESULTS_DIR)/$::env(DESIGN_NAME).v
+write_sdc -no_timestamp $::env(RESULTS_DIR)/$::env(DESIGN_NAME).sdc
+
 if {[env_var_exists_and_non_empty CDL_FILES]} {
   cdl read_masters $::env(CDL_FILES)
   cdl out $::env(RESULTS_DIR)/$stem.cdl
diff --git a/flow/scripts/read_liberty.tcl b/flow/scripts/read_liberty.tcl
index 68f36e84..bcae2bc3 100644
--- a/flow/scripts/read_liberty.tcl
+++ b/flow/scripts/read_liberty.tcl
@@ -20,7 +20,11 @@ if {[env_var_exists_and_non_empty CORNERS]} {
 } else {
   ## no corner
   foreach libFile $::env(LIB_FILES) {
-    read_liberty $libFile
+    if {[file exists [file rootname $libFile].v]} {
+      log_cmd read_verilog [file rootname $libFile].v
+    } else {
+      log_cmd read_liberty $libFile
+    }
   }
 }

[gadfort]

It's possible you don't see anything because OpenROAD will flatten the design so the ports you are looking for might be missing.

[maliberty]

How are you loading the verilog files? Aren't you are just opening the db.

[maliberty]

You show no diff for open.tcl so the .odb file is loaded. The .v file will have no effect as read_verilog won't even be called.

[oharboe]

You show no diff for open.tcl so the .odb file is loaded. The .v file will have no effect as read_verilog won't even be called.

I loaded the .odb file for mock-array and I loaded .v instead of .lib for Element.

So you are saying that if I load .v and .lef for mock-array instead of .odb, it should work?

[maliberty]

There is no separate db for element and so nothing to load for it. There is no lef for mock-array. If you load the verilog for mock-array and Element and avoid loading any odb then you could see the design flat.

[oharboe]

I tried to torture openroad to make this work, but I wasn't able to.

I was able to get sta(not openroad) to show me path that includes details on what is going on in inside the elements with non-registered paths going through the Element.

I believe once #6461 is sorted out, I'll understand better what exactly is going on and how this is supposted to work.

Startpoint: ces_0_0/io_outs_left_REG[0]$_DFF_P_
            (rising edge-triggered flip-flop clocked by clock)
Endpoint: ces_0_4/REG_8$_DFF_P_
          (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 203.96  203.96   clock network delay (propagated)
   0.00  203.96 ^ ces_0_0/io_outs_left_REG[0]$_DFF_P_/CLK (DFFHQNx2_ASAP7_75t_R)
  41.52  245.49 v ces_0_0/io_outs_left_REG[0]$_DFF_P_/QN (DFFHQNx2_ASAP7_75t_R)
   6.91  252.40 ^ ces_0_0/_1090_/Y (INVx2_ASAP7_75t_R)
  12.34  264.74 ^ ces_0_0/output265/Y (BUFx2_ASAP7_75t_R)
  11.50  276.24 ^ ces_0_1/_1287_/Y (BUFx2_ASAP7_75t_R)
  11.50  287.74 ^ ces_0_1/output264/Y (BUFx2_ASAP7_75t_R)
  11.50  299.24 ^ ces_0_2/_1286_/Y (BUFx2_ASAP7_75t_R)
  11.50  310.74 ^ ces_0_2/output263/Y (BUFx2_ASAP7_75t_R)
  11.50  322.24 ^ ces_0_3/_1285_/Y (BUFx2_ASAP7_75t_R)
  11.50  333.74 ^ ces_0_3/output262/Y (BUFx2_ASAP7_75t_R)
  11.57  345.32 ^ ces_0_4/input257/Y (BUFx2_ASAP7_75t_R)
   0.00  345.32 ^ ces_0_4/REG_8$_DFF_P_/D (DFFHQNx2_ASAP7_75t_R)
         345.32   data arrival time

 250.00  250.00   clock clock (rise edge)
 195.69  445.69   clock network delay (propagated)
   1.66  447.35   clock reconvergence pessimism
         447.35 ^ ces_0_4/REG_8$_DFF_P_/CLK (DFFHQNx2_ASAP7_75t_R)
  -5.65  441.70   library setup time
         441.70   data required time
---------------------------------------------------------
         441.70   data required time
        -345.32   data arrival time
---------------------------------------------------------
          96.39   slack (MET)

[oharboe]

This is how far I got, I don't know how to make this work under OpenROAD, I need to use OpenSTA so the technology files and naming differences doesn't get in the way.

The-OpenROAD-Project/OpenROAD-flow-scripts#2654