Status of the project + a few questions

[GiuseppeDiGuglielmo]

hi Alex,
what is the status of the project? are there known issues/limitations, for example

• can this extension be used to test any i2c slave?
• nack doesn't seem to be handle
• is there support for clock stretching?

Thanks,
G.

[GiuseppeDiGuglielmo]

For a classical interface where sda is inout:

module i2c_slave (scl, sda);
  
  input scl;
  inout sda;

endmodule

should the cocotb Master be

i2c_master = I2cMaster(sda=dut.sda, sda_o=dut.sda, scl=dut.scl)

or just

i2c_master = I2cMaster(sda=dut.sda, scl=dut.scl)

?

[alexforencich]

The intention was to support that as

i2c_master = I2cMaster(sda=dut.sda, scl=dut.scl)

But, unfortunately there are bugs in some combination of cocotb, the verilog PLI, and various simulators that seem to prevent that from working. Or, at least I have not yet found a solution that works, nor have I had the time to expolore this in great detail. So, I think at least for the time being, an HDL "shim" implementing tristate buffers will be required to interface with HDL code that uses inout pins.

As an aside, generally I2C components should not use inout pins in the first place, as this makes it impossible to interconnect them internally, and potentially makes testing more complicated. Instead, input and output pins should be used, with tristate buffers instantiated at the edge of the chip.

[alexforencich]

Also, it should work for any I2C components, although I'm not sure if multi-master works properly. Clock stretching should also work. Not sure about nacks; I don't think that will generate an exception, but I think it should be recorded somewhere.

[GiuseppeDiGuglielmo]

@alexforencich as far as I understand a Verilog wrapper of an I2C slave should have some extra logic besides the tristate buffers.

I think I should (or may have to) keep 2 SDA ports (sda and sda_o on your cocotb I2C master) and have a single SDA port that is inout on the slave. Let's ignore for the time being SCL. Do you have any suggestion?