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mir-gen-x86_64.c
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mir-gen-x86_64.c
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/* This file is a part of MIR project.
Copyright (C) 2018-2020 Vladimir Makarov <[email protected]>.
*/
#include <limits.h>
#define HREG_EL(h) h##_HARD_REG
#define REP_SEP ,
enum {
REP8 (HREG_EL, AX, CX, DX, BX, SP, BP, SI, DI),
REP8 (HREG_EL, R8, R9, R10, R11, R12, R13, R14, R15),
REP8 (HREG_EL, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7),
REP8 (HREG_EL, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15),
REP2 (HREG_EL, ST0, ST1),
};
#undef REP_SEP
static const MIR_reg_t MAX_HARD_REG = ST1_HARD_REG;
static const MIR_reg_t FP_HARD_REG = BP_HARD_REG;
static int target_locs_num (MIR_reg_t loc, MIR_type_t type) {
return loc > MAX_HARD_REG && type == MIR_T_LD ? 2 : 1;
}
static inline MIR_reg_t target_nth_loc (MIR_reg_t loc, MIR_type_t type, int n) { return loc + n; }
/* Hard regs not used in machinized code, preferably call used ones. */
const MIR_reg_t TEMP_INT_HARD_REG1 = R10_HARD_REG, TEMP_INT_HARD_REG2 = R11_HARD_REG;
#ifndef _WIN64
const MIR_reg_t TEMP_FLOAT_HARD_REG1 = XMM8_HARD_REG, TEMP_FLOAT_HARD_REG2 = XMM9_HARD_REG;
const MIR_reg_t TEMP_DOUBLE_HARD_REG1 = XMM8_HARD_REG, TEMP_DOUBLE_HARD_REG2 = XMM9_HARD_REG;
#else
const MIR_reg_t TEMP_FLOAT_HARD_REG1 = XMM4_HARD_REG, TEMP_FLOAT_HARD_REG2 = XMM5_HARD_REG;
const MIR_reg_t TEMP_DOUBLE_HARD_REG1 = XMM4_HARD_REG, TEMP_DOUBLE_HARD_REG2 = XMM5_HARD_REG;
#endif
const MIR_reg_t TEMP_LDOUBLE_HARD_REG1 = MIR_NON_HARD_REG;
const MIR_reg_t TEMP_LDOUBLE_HARD_REG2 = MIR_NON_HARD_REG;
static inline int target_hard_reg_type_ok_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
/* For LD we need x87 stack regs and it is too complicated so no
hard register allocation for LD: */
if (type == MIR_T_LD) return FALSE;
return MIR_int_type_p (type) ? hard_reg < XMM0_HARD_REG : hard_reg >= XMM0_HARD_REG;
}
static inline int target_fixed_hard_reg_p (MIR_reg_t hard_reg) {
assert (hard_reg <= MAX_HARD_REG);
return (hard_reg == BP_HARD_REG || hard_reg == SP_HARD_REG || hard_reg == TEMP_INT_HARD_REG1
|| hard_reg == TEMP_INT_HARD_REG2 || hard_reg == TEMP_FLOAT_HARD_REG1
|| hard_reg == TEMP_FLOAT_HARD_REG2 || hard_reg == TEMP_DOUBLE_HARD_REG1
|| hard_reg == TEMP_DOUBLE_HARD_REG2 || hard_reg == ST0_HARD_REG
|| hard_reg == ST1_HARD_REG);
}
static inline int target_call_used_hard_reg_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
#ifndef _WIN64
return !(hard_reg == BX_HARD_REG || (hard_reg >= R12_HARD_REG && hard_reg <= R15_HARD_REG));
#else
return !(hard_reg == BX_HARD_REG || hard_reg == SI_HARD_REG || hard_reg == DI_HARD_REG
|| (hard_reg >= R12_HARD_REG && hard_reg <= R15_HARD_REG)
|| (hard_reg >= XMM6_HARD_REG && hard_reg <= XMM15_HARD_REG));
#endif
}
/* Stack layout (sp refers to the last reserved stack slot address)
from higher address to lower address memory:
| ... | prev func stack frame (start address should be aligned to 16 bytes)
|---------------|
| return pc | value of sp before prologue = start sp hard reg
|---------------|
| old bp | bp for previous func stack frame; new bp refers for here
|---------------|
| reg save | 176 bytes
| area | optional area for vararg func reg save area
|---------------|
| slots assigned| can be absent for small functions (known only after RA)
| to pseudos |
|---------------|
| saved regs | callee saved regs used in the func (known only after RA)
|---------------|
| alloca areas | optional
|---------------|
| slots for | dynamically allocated/deallocated by caller
| passing args |
|---------------|
| spill space | WIN64 only, 32 bytes spill space for register args
|---------------|
size of slots and saved regs is multiple of 16 bytes
*/
#ifndef _WIN64
static const int reg_save_area_size = 176;
static const int spill_space_size = 0;
#else
static const int reg_save_area_size = 0;
static const int spill_space_size = 32;
#endif
static MIR_disp_t target_get_stack_slot_offset (gen_ctx_t gen_ctx, MIR_type_t type,
MIR_reg_t slot) {
/* slot is 0, 1, ... */
return -((MIR_disp_t) (slot + (type == MIR_T_LD ? 2 : 1)) * 8
+ (curr_func_item->u.func->vararg_p ? reg_save_area_size : 0));
}
static const MIR_insn_code_t target_io_dup_op_insn_codes[] = {
/* see possible patterns */
MIR_FADD, MIR_DADD, MIR_LDADD, MIR_SUB, MIR_SUBS, MIR_FSUB, MIR_DSUB,
MIR_LDSUB, MIR_MUL, MIR_MULS, MIR_FMUL, MIR_DMUL, MIR_LDMUL, MIR_DIV,
MIR_DIVS, MIR_UDIV, MIR_FDIV, MIR_DDIV, MIR_LDDIV, MIR_MOD, MIR_MODS,
MIR_UMOD, MIR_UMODS, MIR_AND, MIR_ANDS, MIR_OR, MIR_ORS, MIR_XOR,
MIR_XORS, MIR_LSH, MIR_LSHS, MIR_RSH, MIR_RSHS, MIR_URSH, MIR_URSHS,
MIR_NEG, MIR_NEGS, MIR_FNEG, MIR_DNEG, MIR_LDNEG, MIR_INSN_BOUND,
};
static MIR_insn_code_t get_ext_code (MIR_type_t type) {
switch (type) {
case MIR_T_I8: return MIR_EXT8;
case MIR_T_U8: return MIR_UEXT8;
case MIR_T_I16: return MIR_EXT16;
case MIR_T_U16: return MIR_UEXT16;
case MIR_T_I32: return MIR_EXT32;
case MIR_T_U32: return MIR_UEXT32;
default: return MIR_INVALID_INSN;
}
}
static MIR_reg_t get_fp_arg_reg (size_t fp_arg_num) {
switch (fp_arg_num) {
case 0:
case 1:
case 2:
case 3:
#ifndef _WIN64
case 4:
case 5:
case 6:
case 7:
#endif
return XMM0_HARD_REG + fp_arg_num;
default: return MIR_NON_HARD_REG;
}
}
static MIR_reg_t get_int_arg_reg (size_t int_arg_num) {
switch (int_arg_num
#ifdef _WIN64
+ 2
#endif
) {
case 0: return DI_HARD_REG;
case 1: return SI_HARD_REG;
#ifdef _WIN64
case 2: return CX_HARD_REG;
case 3: return DX_HARD_REG;
#else
case 2: return DX_HARD_REG;
case 3: return CX_HARD_REG;
#endif
case 4: return R8_HARD_REG;
case 5: return R9_HARD_REG;
default: return MIR_NON_HARD_REG;
}
}
static MIR_reg_t get_arg_reg (MIR_type_t arg_type, size_t *int_arg_num, size_t *fp_arg_num,
MIR_insn_code_t *mov_code) {
MIR_reg_t arg_reg;
if (arg_type == MIR_T_LD) {
arg_reg = MIR_NON_HARD_REG;
*mov_code = MIR_LDMOV;
} else if (arg_type == MIR_T_F || arg_type == MIR_T_D) {
arg_reg = get_fp_arg_reg (*fp_arg_num);
(*fp_arg_num)++;
#ifdef _WIN64
(*int_arg_num)++; /* arg slot used by fp, skip int register */
#endif
*mov_code = arg_type == MIR_T_F ? MIR_FMOV : MIR_DMOV;
} else { /* including RBLK */
arg_reg = get_int_arg_reg (*int_arg_num);
#ifdef _WIN64
(*fp_arg_num)++; /* arg slot used by int, skip fp register */
#endif
(*int_arg_num)++;
*mov_code = MIR_MOV;
}
return arg_reg;
}
static void machinize_call (gen_ctx_t gen_ctx, MIR_insn_t call_insn) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_proto_t proto = call_insn->ops[0].u.ref->u.proto;
size_t size, nargs, nops = MIR_insn_nops (ctx, call_insn), start = proto->nres + 2;
size_t int_arg_num = 0, fp_arg_num = 0, xmm_args = 0, mem_size = spill_space_size;
MIR_type_t type, mem_type;
MIR_op_mode_t mode;
MIR_var_t *arg_vars = NULL;
MIR_reg_t arg_reg;
MIR_op_t arg_op, new_arg_op, temp_op, ret_reg_op, mem_op;
MIR_insn_code_t new_insn_code, ext_code;
MIR_insn_t new_insn, prev_insn, next_insn, ext_insn;
MIR_insn_t prev_call_insn = DLIST_PREV (MIR_insn_t, call_insn);
uint32_t n_iregs, n_xregs, n_fregs;
if (call_insn->code == MIR_INLINE) call_insn->code = MIR_CALL;
if (proto->args == NULL) {
nargs = 0;
} else {
gen_assert (nops >= VARR_LENGTH (MIR_var_t, proto->args)
&& (proto->vararg_p || nops - start == VARR_LENGTH (MIR_var_t, proto->args)));
nargs = VARR_LENGTH (MIR_var_t, proto->args);
arg_vars = VARR_ADDR (MIR_var_t, proto->args);
}
if (call_insn->ops[1].mode != MIR_OP_REG && call_insn->ops[1].mode != MIR_OP_HARD_REG) {
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, call_insn->ops[1]);
call_insn->ops[1] = temp_op;
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
for (size_t i = start; i < nops; i++) {
arg_op = call_insn->ops[i];
gen_assert (
arg_op.mode == MIR_OP_REG || arg_op.mode == MIR_OP_HARD_REG
|| (arg_op.mode == MIR_OP_MEM && MIR_all_blk_type_p (arg_op.u.mem.type))
|| (arg_op.mode == MIR_OP_HARD_REG_MEM && MIR_all_blk_type_p (arg_op.u.hard_reg_mem.type)));
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else if (arg_op.mode == MIR_OP_MEM || arg_op.mode == MIR_OP_HARD_REG_MEM) {
type = arg_op.mode == MIR_OP_MEM ? arg_op.u.mem.type : arg_op.u.hard_reg_mem.type;
assert (MIR_all_blk_type_p (type));
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
gen_assert (mode == MIR_OP_INT || mode == MIR_OP_UINT || mode == MIR_OP_FLOAT
|| mode == MIR_OP_DOUBLE || mode == MIR_OP_LDOUBLE);
if (mode == MIR_OP_FLOAT)
(*MIR_get_error_func (ctx)) (MIR_call_op_error,
"passing float variadic arg (should be passed as double)");
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
if (xmm_args < 8 && (type == MIR_T_F || type == MIR_T_D)) xmm_args++;
ext_insn = NULL;
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) { /* extend arg if necessary */
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
ext_insn = MIR_new_insn (ctx, ext_code, temp_op, arg_op);
call_insn->ops[i] = arg_op = temp_op;
}
size = 0;
if (MIR_blk_type_p (type)) {
gen_assert (arg_op.mode == MIR_OP_MEM);
size = (arg_op.u.mem.disp + 7) / 8 * 8;
gen_assert (prev_call_insn != NULL); /* call_insn should not be 1st after simplification */
}
if ((type == MIR_T_BLK2 && get_int_arg_reg (int_arg_num) != MIR_NON_HARD_REG
&& (size <= 8 || get_int_arg_reg (int_arg_num + 1) != MIR_NON_HARD_REG))
|| (type == MIR_T_BLK3 && get_fp_arg_reg (fp_arg_num) != MIR_NON_HARD_REG
&& (size <= 8 || get_fp_arg_reg (fp_arg_num + 1) != MIR_NON_HARD_REG))) {
/* all is passed in gprs or fprs */
MIR_type_t mov_type = type == MIR_T_BLK2 ? MIR_T_I64 : MIR_T_D;
MIR_insn_code_t mov_code;
MIR_reg_t reg2, reg1 = get_arg_reg (mov_type, &int_arg_num, &fp_arg_num, &mov_code);
assert (size <= 16);
new_insn = MIR_new_insn (ctx, mov_code, _MIR_new_hard_reg_op (ctx, reg1),
MIR_new_mem_op (ctx, mov_type, 0, arg_op.u.mem.base, 0, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
setup_call_hard_reg_args (gen_ctx, call_insn, reg1);
call_insn->ops[i].u.mem.base = 0; /* not used anymore */
if (size > 8) {
reg2 = get_arg_reg (mov_type, &int_arg_num, &fp_arg_num, &mov_code);
new_insn = MIR_new_insn (ctx, mov_code, _MIR_new_hard_reg_op (ctx, reg2),
MIR_new_mem_op (ctx, mov_type, 8, arg_op.u.mem.base, 0, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
setup_call_hard_reg_args (gen_ctx, call_insn, reg2);
}
} else if ((type == MIR_T_BLK4 || type == MIR_T_BLK5)
&& get_int_arg_reg (int_arg_num) != MIR_NON_HARD_REG
&& get_fp_arg_reg (fp_arg_num) != MIR_NON_HARD_REG) {
/* gpr and then fpr or fpr and then gpr */
MIR_type_t mov_type1 = type == MIR_T_BLK4 ? MIR_T_I64 : MIR_T_D;
MIR_type_t mov_type2 = type == MIR_T_BLK4 ? MIR_T_D : MIR_T_I64;
MIR_insn_code_t mov_code1, mov_code2;
MIR_reg_t reg1 = get_arg_reg (mov_type1, &int_arg_num, &fp_arg_num, &mov_code1);
MIR_reg_t reg2 = get_arg_reg (mov_type2, &int_arg_num, &fp_arg_num, &mov_code2);
assert (size > 8 && size <= 16);
new_insn = MIR_new_insn (ctx, mov_code1, _MIR_new_hard_reg_op (ctx, reg1),
MIR_new_mem_op (ctx, mov_type1, 0, arg_op.u.mem.base, 0, 1));
setup_call_hard_reg_args (gen_ctx, call_insn, reg1);
call_insn->ops[i].u.mem.base = 0; /* not used anymore */
gen_add_insn_before (gen_ctx, call_insn, new_insn);
new_insn = MIR_new_insn (ctx, mov_code2, _MIR_new_hard_reg_op (ctx, reg2),
MIR_new_mem_op (ctx, mov_type2, 8, arg_op.u.mem.base, 0, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
setup_call_hard_reg_args (gen_ctx, call_insn, reg2);
} else if (MIR_blk_type_p (type)) { /* put block arg on the stack */
MIR_insn_t load_insn;
size_t disp;
int first_p;
if (size > 0 && size <= 2 * 8) { /* upto 2 moves */
disp = 0;
first_p = TRUE;
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
while (size != 0) {
mem_op = MIR_new_mem_op (ctx, MIR_T_I64, disp, arg_op.u.mem.base, 0, 1);
load_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, mem_op);
gen_add_insn_after (gen_ctx, prev_call_insn, load_insn);
disp += 8;
mem_op
= _MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, mem_size, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_MOV, mem_op, temp_op);
mem_size += 8;
size -= 8;
gen_add_insn_after (gen_ctx, load_insn, new_insn);
if (first_p) {
call_insn->ops[i]
= _MIR_new_hard_reg_mem_op (ctx, type, mem_size, SP_HARD_REG, MIR_NON_HARD_REG, 1);
first_p = FALSE;
}
}
} else { /* generate memcpy call before call arg moves */
MIR_reg_t dest_reg;
MIR_op_t freg_op, dest_reg_op, ops[5];
MIR_item_t memcpy_proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, "mir.arg_memcpy.p", 0, NULL, 3,
MIR_T_I64, "dest", MIR_T_I64, "src", MIR_T_I64, "n");
MIR_item_t memcpy_import_item
= _MIR_builtin_func (ctx, curr_func_item->module, "mir.arg_memcpy", memcpy);
freg_op
= MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func));
dest_reg = gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func);
dest_reg_op = MIR_new_reg_op (ctx, dest_reg);
ops[0] = MIR_new_ref_op (ctx, memcpy_proto_item);
ops[1] = freg_op;
ops[2] = _MIR_new_hard_reg_op (ctx, get_int_arg_reg (0));
ops[3] = _MIR_new_hard_reg_op (ctx, get_int_arg_reg (1));
ops[4] = _MIR_new_hard_reg_op (ctx, get_int_arg_reg (2));
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 5, ops);
gen_add_insn_after (gen_ctx, prev_call_insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, ops[4], MIR_new_int_op (ctx, size));
gen_add_insn_after (gen_ctx, prev_call_insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, ops[3], MIR_new_reg_op (ctx, arg_op.u.mem.base));
gen_add_insn_after (gen_ctx, prev_call_insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, ops[2], dest_reg_op);
gen_add_insn_after (gen_ctx, prev_call_insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_ADD, dest_reg_op, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
MIR_new_int_op (ctx, mem_size));
gen_add_insn_after (gen_ctx, prev_call_insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, ops[1], MIR_new_ref_op (ctx, memcpy_import_item));
gen_add_insn_after (gen_ctx, prev_call_insn, new_insn);
call_insn->ops[i] = MIR_new_mem_op (ctx, MIR_T_BLK, arg_op.u.mem.disp, dest_reg, 0, 1);
mem_size += size;
}
} else if ((arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code))
!= MIR_NON_HARD_REG) {
/* put arguments to argument hard regs */
if (ext_insn != NULL) gen_add_insn_before (gen_ctx, call_insn, ext_insn);
if (type != MIR_T_RBLK) {
new_arg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, new_arg_op, arg_op);
} else if (arg_op.mode == MIR_OP_MEM) {
new_insn = MIR_new_insn (ctx, new_insn_code, _MIR_new_hard_reg_op (ctx, arg_reg),
MIR_new_reg_op (ctx, arg_op.u.mem.base));
new_arg_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_RBLK, arg_op.u.mem.disp, arg_reg,
MIR_NON_HARD_REG, 1);
} else {
assert (arg_op.mode == MIR_OP_HARD_REG_MEM);
new_insn = MIR_new_insn (ctx, new_insn_code, _MIR_new_hard_reg_op (ctx, arg_reg),
_MIR_new_hard_reg_op (ctx, arg_op.u.hard_reg_mem.base));
new_arg_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_RBLK, arg_op.u.hard_reg_mem.disp, arg_reg,
MIR_NON_HARD_REG, 1);
}
gen_add_insn_before (gen_ctx, call_insn, new_insn);
call_insn->ops[i] = new_arg_op;
#ifdef _WIN64
/* copy fp reg varargs into corresponding int regs */
if (proto->vararg_p && type == MIR_T_D) {
gen_assert (int_arg_num > 0 && int_arg_num <= 4);
arg_reg = get_int_arg_reg (int_arg_num - 1);
setup_call_hard_reg_args (gen_ctx, call_insn, arg_reg);
/* mir does not support moving fp to int regs directly, spill and load them instead */
mem_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_D, 8, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_DMOV, mem_op, arg_op);
gen_add_insn_before (gen_ctx, call_insn, new_insn);
mem_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 8, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_MOV, _MIR_new_hard_reg_op (ctx, arg_reg), mem_op);
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
#endif
} else { /* put arguments on the stack */
if (type == MIR_T_RBLK) {
assert (arg_op.mode == MIR_OP_MEM || arg_op.mode == MIR_OP_HARD_REG_MEM);
arg_op = arg_op.mode == MIR_OP_MEM ? MIR_new_reg_op (ctx, arg_op.u.mem.base)
: _MIR_new_hard_reg_op (ctx, arg_op.u.hard_reg_mem.base);
}
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code
= (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV : type == MIR_T_LD ? MIR_LDMOV : MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type, mem_size, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, new_insn_code, mem_op, arg_op);
gen_assert (prev_call_insn != NULL); /* call_insn should not be 1st after simplification */
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
prev_insn = DLIST_PREV (MIR_insn_t, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, prev_insn, next_insn, call_insn);
call_insn->ops[i] = mem_op;
mem_size += type == MIR_T_LD ? 16 : 8;
if (ext_insn != NULL) gen_add_insn_after (gen_ctx, prev_call_insn, ext_insn);
}
}
#ifndef _WIN64
if (proto->vararg_p) {
setup_call_hard_reg_args (gen_ctx, call_insn, AX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, _MIR_new_hard_reg_op (ctx, AX_HARD_REG),
MIR_new_int_op (ctx, xmm_args));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
#else
if (proto->nres > 1)
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"Windows x86-64 doesn't support multiple return values");
#endif
n_iregs = n_xregs = n_fregs = 0;
for (size_t i = 0; i < proto->nres; i++) {
ret_reg_op = call_insn->ops[i + 2];
gen_assert (ret_reg_op.mode == MIR_OP_REG || ret_reg_op.mode == MIR_OP_HARD_REG);
if (proto->res_types[i] == MIR_T_F && n_xregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_FMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_xregs == 0 ? XMM0_HARD_REG : XMM1_HARD_REG));
n_xregs++;
} else if (proto->res_types[i] == MIR_T_D && n_xregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_DMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_xregs == 0 ? XMM0_HARD_REG : XMM1_HARD_REG));
n_xregs++;
} else if (proto->res_types[i] == MIR_T_LD && n_fregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_LDMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_fregs == 0 ? ST0_HARD_REG : ST1_HARD_REG));
n_fregs++;
} else if (n_iregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_iregs == 0 ? AX_HARD_REG : DX_HARD_REG));
n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"x86-64 can not handle this combination of return values");
}
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
call_insn->ops[i + 2] = new_insn->ops[1];
if ((ext_code = get_ext_code (proto->res_types[i])) != MIR_INVALID_INSN) {
MIR_insert_insn_after (ctx, curr_func_item, new_insn,
MIR_new_insn (ctx, ext_code, ret_reg_op, ret_reg_op));
new_insn = DLIST_NEXT (MIR_insn_t, new_insn);
}
create_new_bb_insns (gen_ctx, call_insn, DLIST_NEXT (MIR_insn_t, new_insn), call_insn);
}
if (mem_size != 0) { /* allocate/deallocate stack for args passed on stack */
mem_size = (mem_size + 15) / 16 * 16; /* make it of several 16 bytes */
new_insn
= MIR_new_insn (ctx, MIR_SUB, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, prev_call_insn, next_insn, call_insn);
new_insn
= MIR_new_insn (ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, call_insn, next_insn, call_insn);
}
}
static float mir_ui2f (uint64_t i) { return i; }
static double mir_ui2d (uint64_t i) { return i; }
static long double mir_ui2ld (uint64_t i) { return i; }
static int64_t mir_ld2i (long double ld) { return ld; }
static const char *UI2F = "mir.ui2f";
static const char *UI2D = "mir.ui2d";
static const char *UI2LD = "mir.ui2ld";
static const char *LD2I = "mir.ld2i";
static const char *UI2F_P = "mir.ui2f.p";
static const char *UI2D_P = "mir.ui2d.p";
static const char *UI2LD_P = "mir.ui2ld.p";
static const char *LD2I_P = "mir.ld2i.p";
static const char *VA_ARG_P = "mir.va_arg.p";
static const char *VA_ARG = "mir.va_arg";
static const char *VA_BLOCK_ARG_P = "mir.va_block_arg.p";
static const char *VA_BLOCK_ARG = "mir.va_block_arg";
static void get_builtin (gen_ctx_t gen_ctx, MIR_insn_code_t code, MIR_item_t *proto_item,
MIR_item_t *func_import_item) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_type_t res_type;
*func_import_item = *proto_item = NULL; /* to remove uninitialized warning */
switch (code) {
case MIR_UI2F:
res_type = MIR_T_F;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2F_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2F, mir_ui2f);
break;
case MIR_UI2D:
res_type = MIR_T_D;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2D_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2D, mir_ui2d);
break;
case MIR_UI2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2LD, mir_ui2ld);
break;
case MIR_LD2I:
res_type = MIR_T_I64;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2I_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2I, mir_ld2i);
break;
case MIR_VA_ARG:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, VA_ARG_P, 1, &res_type, 2,
MIR_T_I64, "va", MIR_T_I64, "type");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, VA_ARG, va_arg_builtin);
break;
case MIR_VA_BLOCK_ARG:
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, VA_BLOCK_ARG_P, 0, NULL, 4, MIR_T_I64,
"res", MIR_T_I64, "va", MIR_T_I64, "size", MIR_T_I64, "t");
*func_import_item
= _MIR_builtin_func (ctx, curr_func_item->module, VA_BLOCK_ARG, va_block_arg_builtin);
break;
default: assert (FALSE);
}
}
static void gen_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_insn_code_t code, MIR_op_t dst_op,
MIR_op_t src_op) {
gen_add_insn_before (gen_ctx, anchor, MIR_new_insn (gen_ctx->ctx, code, dst_op, src_op));
}
DEF_VARR (int);
DEF_VARR (uint8_t);
DEF_VARR (uint64_t);
struct insn_pattern_info {
int start, num;
};
typedef struct insn_pattern_info insn_pattern_info_t;
DEF_VARR (insn_pattern_info_t);
struct const_ref {
size_t pc; /* where rel32 address should be in code */
size_t next_insn_disp; /* displacement of the next insn */
size_t const_num;
};
typedef struct const_ref const_ref_t;
DEF_VARR (const_ref_t);
struct label_ref {
int abs_addr_p;
size_t label_val_disp, next_insn_disp;
MIR_label_t label;
};
typedef struct label_ref label_ref_t;
DEF_VARR (label_ref_t);
DEF_VARR (MIR_code_reloc_t);
#define MOVDQA_CODE 0
struct target_ctx {
unsigned char alloca_p, block_arg_func_p, leaf_p;
int start_sp_from_bp_offset;
VARR (int) * pattern_indexes;
VARR (insn_pattern_info_t) * insn_pattern_info;
VARR (uint8_t) * result_code;
VARR (uint64_t) * const_pool;
VARR (const_ref_t) * const_refs;
VARR (label_ref_t) * label_refs;
VARR (uint64_t) * abs_address_locs;
VARR (MIR_code_reloc_t) * relocs;
};
#define alloca_p gen_ctx->target_ctx->alloca_p
#define block_arg_func_p gen_ctx->target_ctx->block_arg_func_p
#define leaf_p gen_ctx->target_ctx->leaf_p
#define start_sp_from_bp_offset gen_ctx->target_ctx->start_sp_from_bp_offset
#define pattern_indexes gen_ctx->target_ctx->pattern_indexes
#define insn_pattern_info gen_ctx->target_ctx->insn_pattern_info
#define result_code gen_ctx->target_ctx->result_code
#define const_pool gen_ctx->target_ctx->const_pool
#define const_refs gen_ctx->target_ctx->const_refs
#define label_refs gen_ctx->target_ctx->label_refs
#define abs_address_locs gen_ctx->target_ctx->abs_address_locs
#define relocs gen_ctx->target_ctx->relocs
static void prepend_insn (gen_ctx_t gen_ctx, MIR_insn_t new_insn) {
MIR_prepend_insn (gen_ctx->ctx, curr_func_item, new_insn);
create_new_bb_insns (gen_ctx, NULL, DLIST_NEXT (MIR_insn_t, new_insn), NULL);
}
static void target_machinize (gen_ctx_t gen_ctx) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func;
MIR_type_t type, mem_type, res_type;
MIR_insn_code_t code, new_insn_code;
MIR_insn_t insn, next_insn, new_insn;
MIR_reg_t ret_reg, arg_reg;
MIR_op_t ret_reg_op, arg_reg_op, mem_op;
size_t i, blk_size, int_arg_num = 0, fp_arg_num = 0, mem_size = spill_space_size;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
block_arg_func_p = FALSE;
start_sp_from_bp_offset = 8;
for (i = 0; i < func->nargs; i++) {
/* Argument extensions is already done in simplify */
/* Prologue: generate arg_var = hard_reg|stack mem|stack addr ... */
type = VARR_GET (MIR_var_t, func->vars, i).type;
blk_size = MIR_blk_type_p (type) ? (VARR_GET (MIR_var_t, func->vars, i).size + 7) / 8 * 8 : 0;
if ((type == MIR_T_BLK2 && get_int_arg_reg (int_arg_num) != MIR_NON_HARD_REG
&& (blk_size <= 8 || get_int_arg_reg (int_arg_num + 1) != MIR_NON_HARD_REG))
|| (type == MIR_T_BLK3 && get_fp_arg_reg (fp_arg_num) != MIR_NON_HARD_REG
&& (blk_size <= 8 || get_fp_arg_reg (fp_arg_num + 1) != MIR_NON_HARD_REG))) {
/* all is passed in gprs or fprs */
MIR_type_t mov_type = type == MIR_T_BLK2 ? MIR_T_I64 : MIR_T_D;
MIR_insn_code_t mov_code1, mov_code2;
MIR_reg_t reg2, reg1 = get_arg_reg (mov_type, &int_arg_num, &fp_arg_num, &mov_code1);
assert (blk_size <= 16);
if (blk_size > 8) {
reg2 = get_arg_reg (mov_type, &int_arg_num, &fp_arg_num, &mov_code2);
new_insn = MIR_new_insn (ctx, mov_code1, MIR_new_mem_op (ctx, mov_type, 8, i + 1, 0, 1),
_MIR_new_hard_reg_op (ctx, reg2));
prepend_insn (gen_ctx, new_insn);
}
new_insn = MIR_new_insn (ctx, mov_code1, MIR_new_mem_op (ctx, mov_type, 0, i + 1, 0, 1),
_MIR_new_hard_reg_op (ctx, reg1));
prepend_insn (gen_ctx, new_insn);
new_insn = MIR_new_insn (ctx, MIR_ALLOCA, MIR_new_reg_op (ctx, i + 1),
MIR_new_int_op (ctx, blk_size));
prepend_insn (gen_ctx, new_insn);
} else if ((type == MIR_T_BLK4 || type == MIR_T_BLK5)
&& get_int_arg_reg (int_arg_num) != MIR_NON_HARD_REG
&& get_fp_arg_reg (fp_arg_num) != MIR_NON_HARD_REG) {
/* gpr and then fpr or fpr and then gpr */
MIR_type_t mov_type1 = type == MIR_T_BLK4 ? MIR_T_I64 : MIR_T_D;
MIR_type_t mov_type2 = type == MIR_T_BLK4 ? MIR_T_D : MIR_T_I64;
MIR_insn_code_t mov_code1, mov_code2;
MIR_reg_t reg1 = get_arg_reg (mov_type1, &int_arg_num, &fp_arg_num, &mov_code1);
MIR_reg_t reg2 = get_arg_reg (mov_type2, &int_arg_num, &fp_arg_num, &mov_code2);
assert (blk_size > 8 && blk_size <= 16);
new_insn = MIR_new_insn (ctx, mov_code2, MIR_new_mem_op (ctx, mov_type2, 8, i + 1, 0, 1),
_MIR_new_hard_reg_op (ctx, reg2));
prepend_insn (gen_ctx, new_insn);
new_insn = MIR_new_insn (ctx, mov_code1, MIR_new_mem_op (ctx, mov_type1, 0, i + 1, 0, 1),
_MIR_new_hard_reg_op (ctx, reg1));
prepend_insn (gen_ctx, new_insn);
new_insn = MIR_new_insn (ctx, MIR_ALLOCA, MIR_new_reg_op (ctx, i + 1),
MIR_new_int_op (ctx, blk_size));
prepend_insn (gen_ctx, new_insn);
} else if (MIR_blk_type_p (type)) {
block_arg_func_p = TRUE;
new_insn = MIR_new_insn (ctx, MIR_ADD, MIR_new_reg_op (ctx, i + 1),
_MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, mem_size + 8 /* ret */
+ start_sp_from_bp_offset));
prepend_insn (gen_ctx, new_insn);
mem_size += blk_size;
} else if ((arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code))
!= MIR_NON_HARD_REG) {
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, MIR_new_reg_op (ctx, i + 1), arg_reg_op);
prepend_insn (gen_ctx, new_insn);
} else {
/* arg is on the stack */
block_arg_func_p = TRUE;
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code
= (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV : type == MIR_T_LD ? MIR_LDMOV : MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type,
mem_size + 8 /* ret */
+ start_sp_from_bp_offset,
FP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, new_insn_code, MIR_new_reg_op (ctx, i + 1), mem_op);
prepend_insn (gen_ctx, new_insn);
mem_size += type == MIR_T_LD ? 16 : 8;
}
}
alloca_p = FALSE;
leaf_p = TRUE;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (code == MIR_UI2F || code == MIR_UI2D || code == MIR_UI2LD || code == MIR_LD2I) {
/* Use a builtin func call: mov freg, func ref; call proto, freg, res_reg, op_reg */
MIR_item_t proto_item, func_import_item;
MIR_op_t freg_op, res_reg_op = insn->ops[0], op_reg_op = insn->ops[1], ops[4];
get_builtin (gen_ctx, code, &proto_item, &func_import_item);
assert (res_reg_op.mode == MIR_OP_REG && op_reg_op.mode == MIR_OP_REG);
freg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = res_reg_op;
ops[3] = op_reg_op;
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 4, ops);
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_delete_insn (gen_ctx, insn);
} else if (code == MIR_VA_START) {
MIR_op_t treg_op
= MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func));
MIR_op_t va_op = insn->ops[0];
MIR_reg_t va_reg;
#ifndef _WIN64
int gp_offset = 0, fp_offset = 48, mem_offset = 0;
MIR_var_t var;
assert (func->vararg_p && (va_op.mode == MIR_OP_REG || va_op.mode == MIR_OP_HARD_REG));
for (uint32_t i = 0; i < func->nargs; i++) {
var = VARR_GET (MIR_var_t, func->vars, i);
if (var.type == MIR_T_F || var.type == MIR_T_D) {
fp_offset += 16;
if (gp_offset >= 176) mem_offset += 8;
} else if (var.type == MIR_T_LD) {
mem_offset += 16;
} else if (MIR_blk_type_p (var.type)) {
mem_offset += var.size;
} else { /* including RBLK */
gp_offset += 8;
if (gp_offset >= 48) mem_offset += 8;
}
}
va_reg = va_op.mode == MIR_OP_REG ? va_op.u.reg : va_op.u.hard_reg;
/* Insns can be not simplified as soon as they match a machine insn. */
/* mem32[va_reg] = gp_offset; mem32[va_reg] = fp_offset */
gen_mov (gen_ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_U32, 0, va_reg, 0, 1),
MIR_new_int_op (ctx, gp_offset));
next_insn = DLIST_PREV (MIR_insn_t, insn);
gen_mov (gen_ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_U32, 4, va_reg, 0, 1),
MIR_new_int_op (ctx, fp_offset));
/* overflow_arg_area_reg: treg = start sp + 8 + mem_offset; mem64[va_reg + 8] = treg */
new_insn
= MIR_new_insn (ctx, MIR_ADD, treg_op, _MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, 8 /*ret*/ + mem_offset + start_sp_from_bp_offset));
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_mov (gen_ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 8, va_reg, 0, 1), treg_op);
/* reg_save_area: treg = start sp - reg_save_area_size; mem64[va_reg + 16] = treg */
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, _MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, -reg_save_area_size));
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_mov (gen_ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 16, va_reg, 0, 1), treg_op);
#else
block_arg_func_p = TRUE;
/* spill reg args */
mem_size = 8 /*ret*/ + start_sp_from_bp_offset;
for (int i = 0; i < 4; i++) {
arg_reg = get_int_arg_reg (i);
mem_op
= _MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, mem_size, FP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_MOV, mem_op, _MIR_new_hard_reg_op (ctx, arg_reg));
gen_add_insn_before (gen_ctx, insn, new_insn);
mem_size += 8;
}
/* init va_list */
mem_size = 8 /*ret*/ + start_sp_from_bp_offset + func->nargs * 8;
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, _MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, mem_size));
gen_add_insn_before (gen_ctx, insn, new_insn);
va_reg = va_op.mode == MIR_OP_REG ? va_op.u.reg : va_op.u.hard_reg;
gen_mov (gen_ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 0, va_reg, 0, 1), treg_op);
#endif
gen_delete_insn (gen_ctx, insn);
} else if (code == MIR_VA_END) { /* do nothing */
gen_delete_insn (gen_ctx, insn);
} else if (code == MIR_VA_ARG || code == MIR_VA_BLOCK_ARG) {
#ifndef _WIN64
/* Use a builtin func call:
mov func_reg, func ref; [mov reg3, type;] call proto, func_reg, res_reg, va_reg,
reg3 */
MIR_item_t proto_item, func_import_item;
MIR_op_t ops[6], func_reg_op, reg_op3;
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], op3 = insn->ops[2];
get_builtin (gen_ctx, code, &proto_item, &func_import_item);
assert (res_reg_op.mode == MIR_OP_REG && va_reg_op.mode == MIR_OP_REG
&& op3.mode == (code == MIR_VA_ARG ? MIR_OP_MEM : MIR_OP_REG));
func_reg_op
= MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func));
reg_op3 = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, func_reg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, insn, new_insn);
if (code == MIR_VA_ARG) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, reg_op3, MIR_new_int_op (ctx, (int64_t) op3.u.mem.type));
op3 = reg_op3;
gen_add_insn_before (gen_ctx, insn, new_insn);
}
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = func_reg_op;
ops[2] = res_reg_op;
ops[3] = va_reg_op;
ops[4] = op3;
if (code == MIR_VA_BLOCK_ARG) ops[5] = insn->ops[3];
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, code == MIR_VA_ARG ? 5 : 6, ops);
gen_add_insn_before (gen_ctx, insn, new_insn);
#else
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], mem_op = insn->ops[2], treg_op;
assert (res_reg_op.mode == MIR_OP_REG && va_reg_op.mode == MIR_OP_REG
&& mem_op.mode == MIR_OP_MEM);
/* load and increment va pointer */
treg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func));
gen_mov (gen_ctx, insn, MIR_MOV, treg_op,
MIR_new_mem_op (ctx, MIR_T_I64, 0, va_reg_op.u.reg, 0, 1));
new_insn = MIR_new_insn (ctx, MIR_MOV, res_reg_op, treg_op);
gen_add_insn_before (gen_ctx, insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, treg_op, MIR_new_int_op (ctx, 8));
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_mov (gen_ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 0, va_reg_op.u.reg, 0, 1),
treg_op);
#endif
gen_delete_insn (gen_ctx, insn);
} else if (MIR_call_code_p (code)) {
machinize_call (gen_ctx, insn);
leaf_p = FALSE;
} else if (code == MIR_ALLOCA) {
alloca_p = TRUE;
} else if (code == MIR_RET) {
/* In simplify we already transformed code for one return insn
and added extension in return (if any). */
uint32_t n_iregs = 0, n_xregs = 0, n_fregs = 0;
#ifdef _WIN64
if (curr_func_item->u.func->nres > 1)
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"Windows x86-64 doesn't support multiple return values");
#endif
assert (curr_func_item->u.func->nres == MIR_insn_nops (ctx, insn));
for (size_t i = 0; i < curr_func_item->u.func->nres; i++) {
assert (insn->ops[i].mode == MIR_OP_REG);
res_type = curr_func_item->u.func->res_types[i];
if ((res_type == MIR_T_F || res_type == MIR_T_D) && n_xregs < 2) {
new_insn_code = res_type == MIR_T_F ? MIR_FMOV : MIR_DMOV;
ret_reg = n_xregs++ == 0 ? XMM0_HARD_REG : XMM1_HARD_REG;
} else if (res_type == MIR_T_LD && n_fregs < 2) { // ???
new_insn_code = MIR_LDMOV;
ret_reg = n_fregs == 0 ? ST0_HARD_REG : ST1_HARD_REG;
n_fregs++;
} else if (n_iregs < 2) {
new_insn_code = MIR_MOV;
ret_reg = n_iregs++ == 0 ? AX_HARD_REG : DX_HARD_REG;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"x86-64 can not handle this combination of return values");
}
ret_reg_op = _MIR_new_hard_reg_op (ctx, ret_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, ret_reg_op, insn->ops[i]);
gen_add_insn_before (gen_ctx, insn, new_insn);
insn->ops[i] = ret_reg_op;
}
} else if (code == MIR_LSH || code == MIR_RSH || code == MIR_URSH || code == MIR_LSHS
|| code == MIR_RSHS || code == MIR_URSHS) {
/* We can access only cl as shift register: */
MIR_op_t creg_op = _MIR_new_hard_reg_op (ctx, CX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, creg_op, insn->ops[2]);
gen_add_insn_before (gen_ctx, insn, new_insn);
insn->ops[2] = creg_op;
} else if (code == MIR_DIV || code == MIR_UDIV || code == MIR_DIVS || code == MIR_UDIVS) {
/* Divide uses ax/dx as operands: */
MIR_op_t areg_op = _MIR_new_hard_reg_op (ctx, AX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, areg_op, insn->ops[1]);
gen_add_insn_before (gen_ctx, insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, insn->ops[0], areg_op);
gen_add_insn_after (gen_ctx, insn, new_insn);
insn->ops[0] = insn->ops[1] = areg_op;
} else if (code == MIR_MOD || code == MIR_UMOD || code == MIR_MODS || code == MIR_UMODS) {
/* Divide uses ax/dx as operands: */
MIR_op_t areg_op = _MIR_new_hard_reg_op (ctx, AX_HARD_REG);
MIR_op_t dreg_op = _MIR_new_hard_reg_op (ctx, DX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, areg_op, insn->ops[1]);
gen_add_insn_before (gen_ctx, insn, new_insn);
insn->ops[1] = areg_op;
new_insn = MIR_new_insn (ctx, MIR_MOV, insn->ops[0], dreg_op);
gen_add_insn_after (gen_ctx, insn, new_insn);
insn->ops[0] = dreg_op;
} else if (code == MIR_EQ || code == MIR_NE || code == MIR_LT || code == MIR_ULT
|| code == MIR_LE || code == MIR_ULE || code == MIR_GT || code == MIR_UGT
|| code == MIR_GE || code == MIR_UGE || code == MIR_EQS || code == MIR_NES
|| code == MIR_LTS || code == MIR_ULTS || code == MIR_LES || code == MIR_ULES
|| code == MIR_GTS || code == MIR_UGTS || code == MIR_GES || code == MIR_UGES
|| code == MIR_FEQ || code == MIR_FNE || code == MIR_FLT || code == MIR_FLE
|| code == MIR_FGT || code == MIR_FGE || code == MIR_DEQ || code == MIR_DNE
|| code == MIR_DLT || code == MIR_DLE || code == MIR_DGT || code == MIR_DGE) {
/* We can access only 4 regs in setxx -- use ax as the result: */
MIR_op_t areg_op = _MIR_new_hard_reg_op (ctx, AX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, insn->ops[0], areg_op);
gen_add_insn_after (gen_ctx, insn, new_insn);
insn->ops[0] = areg_op;
}
}
}
static void isave (gen_ctx_t gen_ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
MIR_context_t ctx = gen_ctx->ctx;
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, disp, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, hard_reg));
}
static void dsave (gen_ctx_t gen_ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
MIR_context_t ctx = gen_ctx->ctx;
gen_mov (gen_ctx, anchor, MIR_DMOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_D, disp, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, hard_reg));
}
static void target_make_prolog_epilog (gen_ctx_t gen_ctx, bitmap_t used_hard_regs,
size_t stack_slots_num) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func;
MIR_insn_t anchor, new_insn;
MIR_op_t sp_reg_op, fp_reg_op;
int64_t bp_saved_reg_offset, offset;
size_t i, service_area_size, saved_hard_regs_size, stack_slots_size, block_size;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
for (i = saved_hard_regs_size = 0; i <= R15_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i, MIR_T_UNDEF) && bitmap_bit_p (used_hard_regs, i))
saved_hard_regs_size += 8;
#ifdef _WIN64
for (; i <= XMM15_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i, MIR_T_UNDEF) && bitmap_bit_p (used_hard_regs, i))
saved_hard_regs_size += 16;
#endif
if (leaf_p && !alloca_p && !block_arg_func_p && saved_hard_regs_size == 0 && !func->vararg_p
&& stack_slots_num == 0)
return;
sp_reg_op = _MIR_new_hard_reg_op (ctx, SP_HARD_REG);
fp_reg_op = _MIR_new_hard_reg_op (ctx, FP_HARD_REG);
/* Prologue: */
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
new_insn
= MIR_new_insn (ctx, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, -8, SP_HARD_REG, MIR_NON_HARD_REG, 1),
fp_reg_op);
gen_add_insn_before (gen_ctx, anchor, new_insn); /* -8(sp) = bp */
/* Use add for matching LEA: */
new_insn = MIR_new_insn (ctx, MIR_ADD, fp_reg_op, sp_reg_op, MIR_new_int_op (ctx, -8));
gen_add_insn_before (gen_ctx, anchor, new_insn); /* bp = sp - 8 */
service_area_size = func->vararg_p ? reg_save_area_size + 8 : 8;
stack_slots_size = stack_slots_num * 8;
/* stack slots, and saved regs as multiple of 16 bytes: */
block_size = (stack_slots_size + saved_hard_regs_size + 15) / 16 * 16;
new_insn = MIR_new_insn (ctx, MIR_SUB, sp_reg_op, sp_reg_op,
MIR_new_int_op (ctx, block_size + service_area_size));
gen_add_insn_before (gen_ctx, anchor, new_insn); /* sp -= block size + service_area_size */
bp_saved_reg_offset = block_size;
#ifndef _WIN64
if (func->vararg_p) {
offset = block_size;
isave (gen_ctx, anchor, offset, DI_HARD_REG);
isave (gen_ctx, anchor, offset + 8, SI_HARD_REG);
isave (gen_ctx, anchor, offset + 16, DX_HARD_REG);
isave (gen_ctx, anchor, offset + 24, CX_HARD_REG);
isave (gen_ctx, anchor, offset + 32, R8_HARD_REG);
isave (gen_ctx, anchor, offset + 40, R9_HARD_REG);
dsave (gen_ctx, anchor, offset + 48, XMM0_HARD_REG);
dsave (gen_ctx, anchor, offset + 64, XMM1_HARD_REG);