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LAB_1.gise
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LAB_1.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="LAB_1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="full_adder.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="full_adder.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="full_adder.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="full_adder.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="full_adder.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="full_adder.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="full_adder.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="full_adder.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="full_adder.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="full_adder.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="full_adder.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="full_adder.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="full_adder.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="full_adder.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="full_adder.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="full_adder.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="full_adder.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="full_adder.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="full_adder.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="full_adder_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="full_adder_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="full_adder_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="full_adder_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="full_adder_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="full_adder_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="full_adder_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="full_adder_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="full_adder_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="full_adder_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="full_adder_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="full_adder_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="full_adder_summary.xml"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="full_adder_testbench_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="full_adder_testbench_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="full_adder_testbench_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="full_adder_testbench_stx_beh.prj"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="full_adder_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="full_adder_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1598024028" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1598024028">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598024028" xil_pn:in_ck="2660754033316920906" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1598024028">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="and_gate.vhd"/>
<outfile xil_pn:name="full_adder.vhd"/>
<outfile xil_pn:name="full_adder_testbench.vhd"/>
<outfile xil_pn:name="half_adder.vhd"/>
<outfile xil_pn:name="or_gate.vhd"/>
<outfile xil_pn:name="xor_gate.vhd"/>
</transform>
<transform xil_pn:end_ts="1598024032" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6990799048316912305" xil_pn:start_ts="1598024032">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598024032" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6099419614146043471" xil_pn:start_ts="1598024032">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022705" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-9216453874733187899" xil_pn:start_ts="1598022705">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598024032" xil_pn:in_ck="2660754033316920906" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1598024032">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="and_gate.vhd"/>
<outfile xil_pn:name="full_adder.vhd"/>
<outfile xil_pn:name="full_adder_testbench.vhd"/>
<outfile xil_pn:name="half_adder.vhd"/>
<outfile xil_pn:name="or_gate.vhd"/>
<outfile xil_pn:name="xor_gate.vhd"/>
</transform>
<transform xil_pn:end_ts="1598024038" xil_pn:in_ck="2660754033316920906" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8720677084523480056" xil_pn:start_ts="1598024032">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="full_adder_testbench_beh.prj"/>
<outfile xil_pn:name="full_adder_testbench_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1598024038" xil_pn:in_ck="3891871549042316640" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8565020085084623061" xil_pn:start_ts="1598024038">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="full_adder_testbench_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7467672759292731427" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-9216453874733187899" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7259838547654645439" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="3206529612922900429" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022205" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3786019697212690191" xil_pn:start_ts="1598022205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022470" xil_pn:in_ck="263206168225801033" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="3862226832165594722" xil_pn:start_ts="1598022456">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="full_adder.lso"/>
<outfile xil_pn:name="full_adder.ngc"/>
<outfile xil_pn:name="full_adder.ngr"/>
<outfile xil_pn:name="full_adder.prj"/>
<outfile xil_pn:name="full_adder.stx"/>
<outfile xil_pn:name="full_adder.syr"/>
<outfile xil_pn:name="full_adder.xst"/>
<outfile xil_pn:name="full_adder_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1598022219" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6015436158939792106" xil_pn:start_ts="1598022219">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598022482" xil_pn:in_ck="4163305304363812440" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7350443551055028374" xil_pn:start_ts="1598022470">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="full_adder.bld"/>
<outfile xil_pn:name="full_adder.ngd"/>
<outfile xil_pn:name="full_adder_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1598022520" xil_pn:in_ck="4163305304363812441" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="2100985583056581773" xil_pn:start_ts="1598022482">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="full_adder.pcf"/>
<outfile xil_pn:name="full_adder_map.map"/>
<outfile xil_pn:name="full_adder_map.mrp"/>
<outfile xil_pn:name="full_adder_map.ncd"/>
<outfile xil_pn:name="full_adder_map.ngm"/>
<outfile xil_pn:name="full_adder_map.xrpt"/>
<outfile xil_pn:name="full_adder_summary.xml"/>
<outfile xil_pn:name="full_adder_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1598022564" xil_pn:in_ck="6351553867279047154" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-2283627392121029586" xil_pn:start_ts="1598022520">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="full_adder.ncd"/>
<outfile xil_pn:name="full_adder.pad"/>
<outfile xil_pn:name="full_adder.par"/>
<outfile xil_pn:name="full_adder.ptwx"/>
<outfile xil_pn:name="full_adder.unroutes"/>
<outfile xil_pn:name="full_adder.xpi"/>
<outfile xil_pn:name="full_adder_pad.csv"/>
<outfile xil_pn:name="full_adder_pad.txt"/>
<outfile xil_pn:name="full_adder_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1598022564" xil_pn:in_ck="4163305304363812309" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1598022547">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="full_adder.twr"/>
<outfile xil_pn:name="full_adder.twx"/>
</transform>
</transforms>
</generated_project>