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uut_ROM.vhd
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uut_ROM.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:27:01 09/22/2020
-- Design Name:
-- Module Name: E:/Education/CA/Lab/LAB_7/LAB_7/uut_ROM.vhd
-- Project Name: LAB_7
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ROM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY uut_ROM IS
END uut_ROM;
ARCHITECTURE behavior OF uut_ROM IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ROM
PORT(
ADDR : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal ADDR : std_logic_vector(1 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal DATA_OUT : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ROM PORT MAP (
ADDR => ADDR,
clk => clk,
DATA_OUT => DATA_OUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
ADDR <= "00";
wait for 100 ns;
for i in 0 to 2 loop
ADDR <= ADDR + "01";
wait for clk_period*5;
end loop;
wait;
end process;
END;