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can you confirm it is possible to use with Verilog VHDL ? i just tried, apparently those languages are supported and I did all the steps and I cant see the text formatted
The text was updated successfully, but these errors were encountered:
can you confirm it is possible to use with Verilog VHDL ? i just tried, apparently those languages are supported and I did all the steps and I cant see the text formatted
The text was updated successfully, but these errors were encountered: