Post HLS Synthesis steps?

[amahpour]

First off, just want to say thank you for putting this together - super awesome.

I built my MNIST example with PyTorch and got it to synthesize in conjunction with Vivado HLS. Now I'm left with a module that I'm not really sure how to use:

module myproject (
        x_V,
        layer6_out_0_V,
        layer6_out_1_V,
        layer6_out_2_V,
        layer6_out_3_V,
        layer6_out_4_V,
        layer6_out_5_V,
        layer6_out_6_V,
        layer6_out_7_V,
        layer6_out_8_V,
        layer6_out_9_V,
        ap_clk,
        ap_rst,
        x_V_ap_vld,
        ap_start,
        layer6_out_0_V_ap_vld,
        layer6_out_1_V_ap_vld,
        layer6_out_2_V_ap_vld,
        layer6_out_3_V_ap_vld,
        layer6_out_4_V_ap_vld,
        layer6_out_5_V_ap_vld,
        layer6_out_6_V_ap_vld,
        layer6_out_7_V_ap_vld,
        layer6_out_8_V_ap_vld,
        layer6_out_9_V_ap_vld,
        ap_done,
        ap_ready,
        ap_idle
);


input  [12543:0] x_V;
output  [7:0] layer6_out_0_V;
output  [7:0] layer6_out_1_V;
output  [7:0] layer6_out_2_V;
output  [7:0] layer6_out_3_V;
output  [7:0] layer6_out_4_V;
output  [7:0] layer6_out_5_V;
output  [7:0] layer6_out_6_V;
output  [7:0] layer6_out_7_V;
output  [7:0] layer6_out_8_V;
output  [7:0] layer6_out_9_V;
input   ap_clk;
input   ap_rst;
input   x_V_ap_vld;
input   ap_start;
output   layer6_out_0_V_ap_vld;
output   layer6_out_1_V_ap_vld;
output   layer6_out_2_V_ap_vld;
output   layer6_out_3_V_ap_vld;
output   layer6_out_4_V_ap_vld;
output   layer6_out_5_V_ap_vld;
output   layer6_out_6_V_ap_vld;
output   layer6_out_7_V_ap_vld;
output   layer6_out_8_V_ap_vld;
output   layer6_out_9_V_ap_vld;
output   ap_done;
output   ap_ready;
output   ap_idle;

Is there a guide or directions on how to interface with the generated module? For example, is the data input little endian or big endian? Is there a timing diagram for the input signals (i.e. x_V_ap_vld and ap_start)? What do all the outputs represent?

Thanks.

[RajeevBotadra]

Hey Ari, generally there are two workflows to deploy the model using HLS4ML depending on whether your FPGA has an onboard coprocessor (PS) - the Vitis/Vivado HLS flow (for all Xilinx FPGAs) and the PYNQ flow (for supported boards with PS, though there are ways to use a host CPU as a PS). There is currently an end-to-end tutorial in the FastML repo covering the PYNQ flow (the demo uses the PYNQ-Z2 board, but you can modify it for any of the PYNQ supported cards following their docs and this guide for Xilinx Alevo cards). We are putting together an end-to-end tutorial on deploying HLS4ML using the Vitis/Vivado flow, I'll notify this thread when it's pushed to the UW ACME docs repository.

[brtsfr]

from my understanding,layer6_out_0to9_Vindicate that you have 10 inference result catagories. And [7:0] indicate that the precision is 8 bits. [12543:0] x_V means you have a huge input. i'm also still learning to use this.

[gioregg]

Hi @amahpour ,

I am in your same situation. Did you find a solution for interpreting the vhdl signals in Vivado and for creating a testbench?

Thank you,

Gio

[gioregg]

Hi @brtsfr ,

I am in your same situation. Did you find a solution for interpreting the vhdl signals in Vivado and for creating a testbench?

Thank you,

Gio

[brtsfr]

nope. in fact i left this since then... i think the key is to figure out control logic.

[bo3z]

Hope this helps: #1059 (comment)

[brtsfr]

cool! It is really helpful. i used to write RTL firmware, so very not familiar with the Vitis HLS codes. Many thanks.

[gioregg]

Hi @amahpour ,

Thanks to @bo3z I have a better understanding now.

The timing diagram can ne done with Vivado by running a simulation through a test bench.

The output represent a multi class classification problem( you have 10 classes). The outputs are on 8 bits, so maybe in you hls4ml definition you have set the precision to ap_fixed=8. The others output signals are vld , which are control signals that tell when the output data are valid for each of the output classes. Then you have the others control signal like ap_done , which is used to tell when the output data is available.

Hope this can help,

Gio