Control signals between layers in the verilog code

[sdenholm]

I'm currently looking at the verilog code generated by hls4ml for my own project. I use network layers with variable processing latencies, and so the processing latency of a layer isn't known at build time.

Currently, when data is passed between layers in the hls4ml code, each layer is triggered (ap_start goes high) according to a counter: in the first cycle layer 0 is active, then in cycle 1 layer 1 is active, and so on. Is there a configuration option in hls4ml that would force the use of the control signals of each layer instead, i.e., ap_start of layer n depends on the ap_done signal of layer n-1?