[bug]: Hardware Simulator still sensitive to order of HDL insturctions

[axelkern]

Tool

Hardware Simulator

Interface

Website (https://nand2tetris.github.io/web-ide)

Contact Details

No response

What happened?

The following code fails the CPU test (in line 17 of CPU.tst). It passes when the register updates are moved to the beginning of the code:

CHIP CPU {
    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).
    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
      // loadA, loadD, writeM
      Not(in=instruction[5], out=notD1);
      Nand(a=notD1, b=instruction[15], out=loadA);
      And(a=instruction[4], b=instruction[15], out=loadD);
      And(a=instruction[3], b=instruction[15], out=writeM);
    
      // ALU x=D, y=select A or M
      Mux16(a=outA, b=inM, sel=instruction[12], out=yAlu);
      ALU(x=outD, y=yAlu, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=outAlu, out=outM, zr=zr, ng=ng);

      // A or C instruction -> select input for A register (Immediate or ALU output)
      Mux16(a[0..14]=instruction[0..14], b=outAlu, sel=instruction[15], out=inA);

      // Jump if C instruction and ((j1 and ng) or (j2 and zr) or (j3 and po))
      Or(a=ng, b=zr, out=ngOrZr); //po=not(ng or zr)
      Not(in=ngOrZr, out=po);
      And(a=instruction[2], b=ng, out=jng);
      And(a=instruction[1], b=zr, out=jzr);
      And(a=instruction[0], b=po, out=jpo);
      Or(a=jng, b=jzr, out=jmp1);
      Or(a=jmp1, b=jpo, out=jmp2);
      And(a=jmp2, b=instruction[15], out=jmp);

      // Update registers
      // !!!
      //  !!! Fails in the web IDE in line 17 of test file. Passes if moved to the beginning of the PARTS section.
      PC(in=outA, load=jmp, inc=true, reset=reset, out[0..14]=pc);
      ARegister(in=inA, load=loadA, out=outA, out[0..14]=addressM);
      DRegister(in=outAlu, load=loadD, out=outD);
}

Additional Comments

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