[BUG] <misalgined access>

[Jiahua-Gong]

Bug Description

obi2ahbm_adapter.sv.. if byte access 24bits , bridge don't split 2 trans

[MikeOpenHWGroup]

Thanks for creating this issue @shanshuixiangyi.

Hi @davideschiavone, I have added both bug and question labels to this issue as I am not sure if this feature is supported by the CVE2. If it is not, then the OBI2AHB bridge does not need to support this. If that is the case, we should clearly document the behavior of the bridge.

[davideschiavone]

hi @MikeOpenHWGroup and @shanshuixiangyi - the CVE2 supports misaligned on the OBI interface, so it is very well possible that the bridge has this bug -

[MikeOpenHWGroup]

Thanks @davideschiavone, I have removed the question label and this is now officially a bug! 😉

Hi @shanshuixiangyi, do you have an example test-program to exercise this?

[Jiahua-Gong]

risc-v load store uint can transmit red select in the pitcture. but bridge can't support this byte condition. I have modified the rtl to support this condition. I am learning how to submit code and then make a fix commit using Git.

[MikeOpenHWGroup]

I am learning how to submit code and then make a fix commit using Git.

Thank you very much @Jiahua-Gong! I notice that the CONTRIBUTING file for this repo is not complete (I will fix that). In the meantime, please review CONTRIBUTING.md in CORE-V-VERIF, especially the Contributor Agreement section.