From faf0ed39a80e732f8fdaa0622cefcb30c047d615 Mon Sep 17 00:00:00 2001
From: Ben Kreis <benjaminkreis@gmail.com>
Date: Mon, 6 Feb 2017 15:12:50 -0600
Subject: [PATCH] Completely blank project that can be version controlled

---
 README.md      |  9 ++++++++-
 build.tcl      | 30 ++++++++++++++++++++++++++++++
 cgn/.gitignore |  0
 hdl/top.vhd    | 43 +++++++++++++++++++++++++++++++++++++++++++
 ucf/.gitignore |  0
 utils.tcl      |  8 ++++++++
 6 files changed, 89 insertions(+), 1 deletion(-)
 create mode 100644 build.tcl
 create mode 100644 cgn/.gitignore
 create mode 100644 hdl/top.vhd
 create mode 100644 ucf/.gitignore
 create mode 100644 utils.tcl

diff --git a/README.md b/README.md
index 57abb44..366be89 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,8 @@
-# ParticleFlow
\ No newline at end of file
+# ParticleFlow
+
+
+After setting up Vivado (settings and licenses):
+```
+vivado -mode batch -source build.tcl
+vivado ParticeFlow/ParticeFlow.xpr &
+```
\ No newline at end of file
diff --git a/build.tcl b/build.tcl
new file mode 100644
index 0000000..52c3cfc
--- /dev/null
+++ b/build.tcl
@@ -0,0 +1,30 @@
+# Source common utilities
+source -notrace utils.tcl
+
+# Location of hdl
+set hdlRoot hdl
+
+# Set the reference directory for source file relative paths (by default the value is scrip\
+t directory path)                                                                           
+set origin_dir "."
+
+# Set the directory path for the original project from where this script was exported       
+set orig_proj_dir "[file normalize "$origin_dir/"]"
+
+# Create project                                                                            
+create_project -force ParticeFlow ./ParticeFlow
+
+# Set the directory path for the new project                                                
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties                                                                    
+set obj [get_projects ParticeFlow]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "part" "xc7vx690tffg1930-2" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+
+add_files -norecurse $hdlRoot/top.vhd
+
+# If successful, "touch" a file so the make utility will know it's done 
+touch {.setup.done}
diff --git a/cgn/.gitignore b/cgn/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/hdl/top.vhd b/hdl/top.vhd
new file mode 100644
index 0000000..f3f15f2
--- /dev/null
+++ b/hdl/top.vhd
@@ -0,0 +1,43 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02/06/2017 11:17:30 AM
+-- Design Name: 
+-- Module Name: top - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+--  Port ( );
+end top;
+
+architecture Behavioral of top is
+
+begin
+
+
+end Behavioral;
diff --git a/ucf/.gitignore b/ucf/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/utils.tcl b/utils.tcl
new file mode 100644
index 0000000..a46fe4c
--- /dev/null
+++ b/utils.tcl
@@ -0,0 +1,8 @@
+# this is a collection of useful project utilities
+
+# implement touch - opens a file updating the time stamp,
+# creating it if it does not exist
+proc touch {f} {
+   set FILEIN [open $f w]
+   close $FILEIN
+}