From 6ab5d6899f9d7e7cd6ebabf2378699ba8ded0053 Mon Sep 17 00:00:00 2001 From: Daniele Lacamera Date: Fri, 13 Oct 2023 15:45:20 +0200 Subject: [PATCH] Fix cppcheck warnings --- hal/hifive1.c | 58 +++++++++++++------------- hal/nxp_p1021.c | 54 ++++++++++++------------ hal/nxp_ppc.h | 32 +++++++-------- hal/skeleton.c | 2 + hal/stm32f4.c | 2 +- hal/stm32f7.c | 2 +- hal/stm32g0.c | 2 +- hal/stm32l5_ns.c | 2 +- hal/stm32u5.c | 2 +- hal/stm32u5_ns.c | 82 ++++++++++++++++++------------------- hal/stm32wb.c | 32 +++++++-------- hal/uart/uart_drv_stm32wb.c | 8 ++-- src/pci.c | 2 +- 13 files changed, 141 insertions(+), 139 deletions(-) diff --git a/hal/hifive1.c b/hal/hifive1.c index 3f9c82308..e694d6c72 100644 --- a/hal/hifive1.c +++ b/hal/hifive1.c @@ -55,9 +55,9 @@ /* QSPI Fields */ #define FESPI_IP_TXWM 0x1 -#define FESPI_RXDATA_FIFO_EMPTY (1 << 31) -#define FESPI_TXDATA_FIFO_FULL (1 << 31) -#define FESPI_FMT_DIR_TX (1 << 3) +#define FESPI_RXDATA_FIFO_EMPTY (1UL << 31) +#define FESPI_TXDATA_FIFO_FULL (1UL << 31) +#define FESPI_FMT_DIR_TX (1UL << 3) #define FESPI_CSMODE_AUTO 0x0UL #define FESPI_CSMODE_HOLD 0x2UL @@ -65,18 +65,18 @@ #define FESPI_FCTRL_MODE_SEL 0x1UL -#define FESPI_FFMT_CMD_EN 0x1 -#define FESPI_FFMT_ADDR_LEN(x) (((x) & 0x7) << 1) -#define FESPI_FFMT_PAD_CNT(x) (((x) & 0xf) << 4) -#define FESPI_FFMT_CMD_PROTO(x) (((x) & 0x3) << 8) -#define FESPI_FFMT_ADDR_PROTO(x) (((x) & 0x3) << 10) -#define FESPI_FFMT_DATA_PROTO(x) (((x) & 0x3) << 12) -#define FESPI_FFMT_CMD_CODE(x) (((x) & 0xff) << 16) -#define FESPI_FFMT_PAD_CODE(x) (((x) & 0xff) << 24) +#define FESPI_FFMT_CMD_EN 0x1UL +#define FESPI_FFMT_ADDR_LEN(x) (((x) & 0x7) << 1UL) +#define FESPI_FFMT_PAD_CNT(x) (((x) & 0xf) << 4UL) +#define FESPI_FFMT_CMD_PROTO(x) (((x) & 0x3) << 8UL) +#define FESPI_FFMT_ADDR_PROTO(x) (((x) & 0x3) << 10UL) +#define FESPI_FFMT_DATA_PROTO(x) (((x) & 0x3) << 12UL) +#define FESPI_FFMT_CMD_CODE(x) (((x) & 0xff) << 16UL) +#define FESPI_FFMT_PAD_CODE(x) (((x) & 0xff) << 24UL) -#define FESPI_SCKDIV_MASK 0xFFF +#define FESPI_SCKDIV_MASK 0xFFFUL -#define FESPI_TXMARK_MASK 0x3 +#define FESPI_TXMARK_MASK 0x3UL /* FESPI_REG_FMT Fields */ /* SPI I/O direction */ @@ -104,11 +104,11 @@ #endif /* SPI flash status fields (from FESPI_READ_STATUS command) */ -#define FESPI_RX_BSY (1 << 0) -#define FESPI_RX_WE (1 << 1) +#define FESPI_RX_BSY (1 << 0UL) +#define FESPI_RX_WE (1 << 1UL) /* QSPI Flash Sector Size */ -#define FESPI_FLASH_SECTOR_SIZE (4 * 1024) +#define FESPI_FLASH_SECTOR_SIZE (4 * 1024UL) /* PRCI Registers */ @@ -135,8 +135,8 @@ #define HFROSCCFG_DIV 0x0000001FUL #define HFROSCCFG_TRIM 0x001F0000UL -#define HFROSCCFG_EN (1UL << 30) -#define HFROSCCFG_READY (1UL << 31) +#define HFROSCCFG_EN (1UL << 30UL) +#define HFROSCCFG_READY (1UL << 31UL) #define HFROSCCFG_DIV_SHIFT(d) ((d << 0) & HFROSCCFG_TRIM) #define HFROSCCFG_TRIM_SHIFT(t) ((t << 16) & HFROSCCFG_TRIM) @@ -154,19 +154,19 @@ #define UART_REG_DIV (*(volatile uint32_t *)(UART0_BASE + 0x18)) /* TXDATA Fields */ -#define UART_TXEN (1 << 0) -#define UART_TXFULL (1 << 31) +#define UART_TXEN (1UL << 0) +#define UART_TXFULL (1UL << 31) /* RXDATA Fields */ -#define UART_RXEN (1 << 0) -#define UART_RXEMPTY (1 << 31) +#define UART_RXEN (1UL << 0) +#define UART_RXEMPTY (1UL << 31) /* TXCTRL Fields */ -#define UART_NSTOP (1 << 1) -#define UART_TXCNT(count) ((0x7 & count) << 16) +#define UART_NSTOP (1UL << 1) +#define UART_TXCNT(count) ((0x7UL & count) << 16) /* IP Fields */ -#define UART_TXWM (1 << 0) +#define UART_TXWM (1UL << 0) /* Configuration Defaults */ @@ -183,16 +183,16 @@ /* PLL Configuration */ /* R and Q are fixed values for this PLL code */ #define PLL_R (1) /* First Divisor: By 2 (takes 16Mhz PLLREF / 2 = 8MHz) */ -#define PLL_F(cpuHz) (((cpuHz / PLLREF_FREQ) * 2) - 1) /* Multiplier */ +#define PLL_F(cpuHz) (((cpuHz / PLLREF_FREQ) * 2U) - 1U) /* Multiplier */ #define PLL_Q (1) /* Second Divisor: By 2 */ /* SPI Serial clock divisor */ -#define FESPI_SCKDIV_DEFAULT 0x03 -#define FESPI_SCKDIV_VAL(cpuHz, flashHz) (cpuHz / ((2 * flashHz) - 1)) +#define FESPI_SCKDIV_DEFAULT 0x03U +#define FESPI_SCKDIV_VAL(cpuHz, flashHz) (cpuHz / ((2U * flashHz) - 1U)) /* UART baud initialize value */ #ifndef UART_BAUD_INIT -#define UART_BAUD_INIT 115200 +#define UART_BAUD_INIT 115200U #endif diff --git a/hal/nxp_p1021.c b/hal/nxp_p1021.c index 749fbdc32..256acdb4b 100644 --- a/hal/nxp_p1021.c +++ b/hal/nxp_p1021.c @@ -194,7 +194,7 @@ static int test_tpm(void); #define UART_LSR_THRE (0x20) /* Transmitter holding register empty */ /* P1021 eLBC (Enhanced Local Bus Controller) - RM 12.3 */ -#define ELBC_BASE (CCSRBAR + 0x5000) +#define ELBC_BASE (CCSRBAR + 0x5000UL) #define ELBC_MAX_BANKS 8 #define ELBC_BANK_SZ 8192 @@ -216,40 +216,40 @@ static int test_tpm(void); #define ELBC_LTEATR ((volatile uint32_t*)(ELBC_BASE + 0xBC)) /* transfer error attributes register */ -#define ELBC_BR_ADDR(n) (((uint32_t)n) & 0xFFFF8000) /* Physical base address - upper 17-bits */ -#define ELBC_BR_PS(n) (((n) & 0x3) << 11) /* port size - 1=8-bit, 2=16-bit */ -#define ELBC_BR_DECC(n) (((n) & 0x3) << 9) /* data error checking - 0=disabled, 1=ECC check enable / gen disabled, 2=ECC check/gen enabled */ -#define ELBC_BR_WP (1 << 8) /* write protect */ -#define ELBC_BR_MSEL(n) (((n) & 0x7) << 5) /* machine select: +#define ELBC_BR_ADDR(n) (((uint32_t)n) & 0xFFFF8000UL) /* Physical base address - upper 17-bits */ +#define ELBC_BR_PS(n) (((n) & 0x3UL) << 11) /* port size - 1=8-bit, 2=16-bit */ +#define ELBC_BR_DECC(n) (((n) & 0x3UL) << 9) /* data error checking - 0=disabled, 1=ECC check enable / gen disabled, 2=ECC check/gen enabled */ +#define ELBC_BR_WP (1UL << 8) /* write protect */ +#define ELBC_BR_MSEL(n) (((n) & 0x7UL) << 5) /* machine select: * 0=GPCM (General Purpose Chip-Select Machine) * 1=FCM (Flash Control Machine), * 4=UPMA, 5=UPMB, 6=UPMC (User Programmable Machines) */ -#define ELBC_BR_V (1 << 0) /* bank valid */ +#define ELBC_BR_V (1UL << 0) /* bank valid */ /* eLBC OR */ #define ELBC_OR_AMASK(n) (((uint32_t)n) & 0xFFFF8000) /* Address mask - upper 17-bits */ /* eLBC OR (FCM) */ -#define ELBC_ORF_BCTLD (1 << 12) /* buffer control disable */ -#define ELBC_ORF_PGS (1 << 10) /* page size 0=512, 1=2048 bytes */ -#define ELBC_ORF_CSCT (1 << 9) /* chip select to command time - TRLX=0 (0=1, 1=4), TRLX=1 (0=2, 1=8) clock cycles */ -#define ELBC_ORF_CST (1 << 8) /* command setup time - TRLX=0 (0=0 or 1=0.25) TRLX=1 (0=0.5 or 1=1) clock cycles */ -#define ELBC_ORF_CHT (1 << 7) /* command hold time - TRLX=0 (0=0.5 or 1=1) TRLX=1 (0=1.5 or 1=2) clock cycles */ -#define ELBC_ORF_SCY(n) (((n) & 0x7) << 4) /* cycle length in bus clocks (0-7 bus clock cycle wait states) */ -#define ELBC_ORF_RST (1 << 3) /* read time setup - read enable asserted 1 clock */ -#define ELBC_ORF_TRLX (1 << 2) /* timing related */ -#define ELBC_ORF_EHTR (1 << 1) /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */ +#define ELBC_ORF_BCTLD (1UL << 12) /* buffer control disable */ +#define ELBC_ORF_PGS (1UL << 10) /* page size 0=512, 1=2048 bytes */ +#define ELBC_ORF_CSCT (1UL << 9) /* chip select to command time - TRLX=0 (0=1, 1=4), TRLX=1 (0=2, 1=8) clock cycles */ +#define ELBC_ORF_CST (1UL << 8) /* command setup time - TRLX=0 (0=0 or 1=0.25) TRLX=1 (0=0.5 or 1=1) clock cycles */ +#define ELBC_ORF_CHT (1UL << 7) /* command hold time - TRLX=0 (0=0.5 or 1=1) TRLX=1 (0=1.5 or 1=2) clock cycles */ +#define ELBC_ORF_SCY(n) (((n) & 0x7UL) << 4) /* cycle length in bus clocks (0-7 bus clock cycle wait states) */ +#define ELBC_ORF_RST (1UL << 3) /* read time setup - read enable asserted 1 clock */ +#define ELBC_ORF_TRLX (1UL << 2) /* timing related */ +#define ELBC_ORF_EHTR (1UL << 1) /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */ /* eLBC OR (GPCM) */ -#define ELBC_ORG_CSCT (1 << 11) -#define ELBC_ORG_XACS (1 << 8) -#define ELBC_ORG_SCY (1 << 4) -#define ELBC_ORG_TRLX (1 << 2) -#define ELBC_ORG_EHTR (1 << 1) -#define ELBC_ORG_EAD (1 << 0) +#define ELBC_ORG_CSCT (1UL << 11) +#define ELBC_ORG_XACS (1UL << 8) +#define ELBC_ORG_SCY (1UL << 4) +#define ELBC_ORG_TRLX (1UL << 2) +#define ELBC_ORG_EHTR (1UL << 1) +#define ELBC_ORG_EAD (1UL << 0) -#define ELBC_LSOR_BANK(n) ((n) & (ELBC_MAX_BANKS-1)) /* flash bank 0-7 */ +#define ELBC_LSOR_BANK(n) ((n) & (ELBC_MAX_BANKS-1UL)) /* flash bank 0-7 */ #define ELBC_LBCR_ABSWP (1 << 19) /* Address byte swap for 16-bit port size */ #define ELBC_LBCR_BMTPS(n) ((n) & 0xF) /* Bus monitor timer prescale */ @@ -257,10 +257,10 @@ static int test_tpm(void); #define ELBC_FMR_CWTO(n) (((n) & 0xF) << 12) /* command wait timeout 0=256 cycles, 15=8,388,608 cycles of LCLK */ #define ELBC_FMR_BOOT (1 << 11) /* flash auto-boot lead mode 0=FCM is op normal, 1=eLBC autoload 4-Kbyte boot block */ #define ELBC_FMR_ECCM (1 << 8) /* ECC mode 0=ECC is checked/calc 6/8 spare, 1=8/10 spare */ -#define ELBC_FMR_AL(n) (((n) & 0x3) << 4) /* address length 0=2 bytes, 1=3 bytes, 2=4 bytes issued for page address */ -#define ELBC_FMR_OP(n) (((n) & 0x3) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */ +#define ELBC_FMR_AL(n) (((n) & 0x3UL) << 4) /* address length 0=2 bytes, 1=3 bytes, 2=4 bytes issued for page address */ +#define ELBC_FMR_OP(n) (((n) & 0x3UL) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */ -#define ELBC_FIR_OP(s,op) ((op) & 0xF) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */ +#define ELBC_FIR_OP(s,op) ((op) & 0xFUL) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */ #define ELBC_FIR_OP_NOP 0 /* No-operation and end of operation sequence */ #define ELBC_FIR_OP_CA 1 /* Issue current column address as set in FPAR, with length set by ORx[PGS] */ #define ELBC_FIR_OP_PA 2 /* Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL] */ @@ -277,7 +277,7 @@ static int test_tpm(void); #define ELBC_FIR_OP_CW1 13 /* Wait for LFRB to return high or time-out, then issue command from FCR[CMD1] */ #define ELBC_FIR_OP_RBW 14 /* Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device into current FCM RAM buffer */ #define ELBC_FIR_OP_RSW 15 /* Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash device into next AS field of MDR */ -#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFF) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */ +#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFFUL) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */ #define ELBC_LCRR_CLKDIV_MASK 0x0000001F #define ELBC_LCRR_CLKDIV_4 0x2 diff --git a/hal/nxp_ppc.h b/hal/nxp_ppc.h index 4ad66c196..240751179 100644 --- a/hal/nxp_ppc.h +++ b/hal/nxp_ppc.h @@ -28,22 +28,22 @@ #define CORE_E500 #define LAW_MAX_ENTRIES 12 - #define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */ + #define CCSRBAR_DEF (0xFF700000UL) /* P1021RM 4.3 default base */ #define CCSRBAR_SIZE BOOKE_PAGESZ_1M #define ENABLE_DDR - #define DDR_SIZE (512 * 1024 * 1024) + #define DDR_SIZE (512UL * 1024UL * 1024UL) /* Memory used for transferring blocks to/from NAND. * Maps to eLBC FCM internal 8KB region (by hardware) */ - #define FLASH_BASE_ADDR 0xFC000000 + #define FLASH_BASE_ADDR 0xFC000000UL #ifdef BUILD_LOADER_STAGE1 /* First stage loader features */ #define ENABLE_L2_CACHE - #define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */ - #define L2SRAM_SIZE (256 * 1024) + #define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */ + #define L2SRAM_SIZE (256UL * 1024UL) #define INITIAL_SRAM_ADDR L2SRAM_ADDR #define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB @@ -55,7 +55,7 @@ #define ENABLE_L2_CACHE /* Relocate CCSRBAR */ - #define CCSRBAR 0xFFE00000 + #define CCSRBAR 0xFFE00000UL #define ENABLE_INTERRUPTS #endif @@ -88,7 +88,7 @@ #define ENABLE_DDR #define DDR_SIZE (2048ULL * 1024ULL * 1024ULL) - #define FLASH_BASE_ADDR 0xEC000000 + #define FLASH_BASE_ADDR 0xEC000000UL #define FLASH_BASE_PHYS_HIGH 0xFULL #define FLASH_LAW_SIZE LAW_SIZE_64MB #define FLASH_TLB_PAGESZ BOOKE_PAGESZ_64M @@ -101,7 +101,7 @@ #define CORE_E6500 #define LAW_MAX_ENTRIES 32 - #define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base */ + #define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */ #define CCSRBAR_SIZE BOOKE_PAGESZ_16M /* relocate to 64-bit 0xE_ */ @@ -111,8 +111,8 @@ #define ENABLE_L1_CACHE #define ENABLE_L2_CACHE - #define L2SRAM_ADDR (0xF8F80000) /* L2 as SRAM */ - #define L2SRAM_SIZE (256 * 1024) + #define L2SRAM_ADDR (0xF8F80000UL) /* L2 as SRAM */ + #define L2SRAM_SIZE (256UL * 1024UL) #define INITIAL_SRAM_ADDR L2SRAM_ADDR #define INITIAL_SRAM_LAW_SZ LAW_SIZE_256KB @@ -122,9 +122,9 @@ #define ENABLE_INTERRUPTS #define ENABLE_DDR - #define DDR_SIZE (8192 * 1024 * 1024) + #define DDR_SIZE (8192UL * 1024UL * 1024UL) - #define FLASH_BASE_ADDR 0xE8000000 + #define FLASH_BASE_ADDR 0xE8000000UL #define FLASH_BASE_PHYS_HIGH 0x0ULL #define FLASH_LAW_SIZE LAW_SIZE_128MB #define FLASH_TLB_PAGESZ BOOKE_PAGESZ_128M @@ -138,10 +138,10 @@ /* boot address */ #ifndef BOOT_ROM_ADDR -#define BOOT_ROM_ADDR 0xFFFFF000 +#define BOOT_ROM_ADDR 0xFFFFF000UL #endif #ifndef BOOT_ROM_SIZE -#define BOOT_ROM_SIZE (4*1024) +#define BOOT_ROM_SIZE (4UL*1024UL) #endif /* reset vector */ @@ -149,7 +149,7 @@ /* CCSRBAR */ #ifndef CCSRBAR_DEF -#define CCSRBAR_DEF 0xFE000000 +#define CCSRBAR_DEF 0xFE000000UL #endif #ifndef CCSRBAR #define CCSRBAR CCSRBAR_DEF @@ -163,7 +163,7 @@ /* DDR */ #ifndef DDR_ADDRESS -#define DDR_ADDRESS 0x00000000 +#define DDR_ADDRESS 0x00000000UL #endif /* L1 */ diff --git a/hal/skeleton.c b/hal/skeleton.c index 30f845baf..29fce5741 100644 --- a/hal/skeleton.c +++ b/hal/skeleton.c @@ -40,6 +40,7 @@ void hal_prepare_boot(void) int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) { + return 0; /* on success. */ } void RAMFUNCTION hal_flash_unlock(void) @@ -52,5 +53,6 @@ void RAMFUNCTION hal_flash_lock(void) int RAMFUNCTION hal_flash_erase(uint32_t address, int len) { + return 0; /* on success. */ } diff --git a/hal/stm32f4.c b/hal/stm32f4.c index c56d586bc..8d95d6b78 100644 --- a/hal/stm32f4.c +++ b/hal/stm32f4.c @@ -84,7 +84,7 @@ #define FLASH_SR_OPERR (1 << 1) #define FLASH_SR_EOP (1 << 0) -#define FLASH_CR_LOCK (uint32_t)(1 << 31) +#define FLASH_CR_LOCK (1UL << 31) #define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_EOPIE (1 << 24) #define FLASH_CR_STRT (1 << 16) diff --git a/hal/stm32f7.c b/hal/stm32f7.c index f16212eb0..85da468e2 100644 --- a/hal/stm32f7.c +++ b/hal/stm32f7.c @@ -86,7 +86,7 @@ #define FLASH_SR_OPERR (1 << 1) #define FLASH_SR_EOP (1 << 0) -#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_LOCK (1UL << 31) #define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_EOPIE (1 << 24) #define FLASH_CR_STRT (1 << 16) diff --git a/hal/stm32g0.c b/hal/stm32g0.c index 21246d869..ee0406df7 100644 --- a/hal/stm32g0.c +++ b/hal/stm32g0.c @@ -80,7 +80,7 @@ #define FLASH_SR_PROGERR (1 << 3) #define FLASH_SR_EOP (1 << 0) /* RM0444 - 3.7.4 - FLASH_SR */ -#define FLASH_CR_LOCK (1 << 31) /* RM0444 - 3.7.5 - FLASH_CR */ +#define FLASH_CR_LOCK (1UL << 31) /* RM0444 - 3.7.5 - FLASH_CR */ #define FLASH_CR_STRT (1 << 16) /* RM0444 - 3.7.5 - FLASH_CR */ #define FLASH_CR_PER (1 << 1) /* RM0444 - 3.7.5 - FLASH_CR */ diff --git a/hal/stm32l5_ns.c b/hal/stm32l5_ns.c index 34e639bde..63b21c8fb 100644 --- a/hal/stm32l5_ns.c +++ b/hal/stm32l5_ns.c @@ -165,7 +165,7 @@ #define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_OBL_LAUNCH (1 << 27) #define FLASH_CR_OPTLOCK (1 << 30) -#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_LOCK (1UL << 31) #define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) #define FLASH_ACR_LATENCY_MASK (0x0F) diff --git a/hal/stm32u5.c b/hal/stm32u5.c index 147408907..1f532ff73 100644 --- a/hal/stm32u5.c +++ b/hal/stm32u5.c @@ -177,7 +177,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len) { uint32_t end_address; uint32_t p; - volatile uint32_t *cr; + volatile uint32_t *cr = &FLASH_NS_CR; flash_clear_errors(0); if (len == 0) diff --git a/hal/stm32u5_ns.c b/hal/stm32u5_ns.c index 150e2a485..55c9e917e 100644 --- a/hal/stm32u5_ns.c +++ b/hal/stm32u5_ns.c @@ -38,24 +38,24 @@ #define FLASH_SECURE_MMAP_BASE (0x0C000000) #define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) /* RM0456 - Table 108 */ -#define RCC_CR_PLL3RDY (1 << 29) -#define RCC_CR_PLL3ON (1 << 28) -#define RCC_CR_PLL2RDY (1 << 27) -#define RCC_CR_PLL2ON (1 << 26) -#define RCC_CR_PLL1RDY (1 << 25) -#define RCC_CR_PLL1ON (1 << 24) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSIRDY (1 << 10) -#define RCC_CR_HSION (1 << 8) -#define RCC_CR_MSIPLLEN (1 << 3) -#define RCC_CR_MSIRDY (1 << 2) -#define RCC_CR_MSISON (1 << 0) +#define RCC_CR_PLL3RDY (1UL << 29) +#define RCC_CR_PLL3ON (1UL << 28) +#define RCC_CR_PLL2RDY (1UL << 27) +#define RCC_CR_PLL2ON (1UL << 26) +#define RCC_CR_PLL1RDY (1UL << 25) +#define RCC_CR_PLL1ON (1UL << 24) +#define RCC_CR_CSSON (1UL << 19) +#define RCC_CR_HSEBYP (1UL << 18) +#define RCC_CR_HSERDY (1UL << 17) +#define RCC_CR_HSEON (1UL << 16) +#define RCC_CR_HSIRDY (1UL << 10) +#define RCC_CR_HSION (1UL << 8) +#define RCC_CR_MSIPLLEN (1UL << 3) +#define RCC_CR_MSIRDY (1UL << 2) +#define RCC_CR_MSISON (1UL << 0) #define RCC_CFGR1 (*(volatile uint32_t *)(RCC_BASE + 0x1C)) /* RM0456 - Table 108 */ -#define RCC_CFGR1_SWS (1 << 2) +#define RCC_CFGR1_SWS (1UL << 2) /*** APB1&2 PRESCALER ***/ #define RCC_APB_PRESCALER_DIV_NONE 0x0 /* 0xx: HCLK not divided */ @@ -78,21 +78,21 @@ #define RCC_CFGR3_PPRE3_SHIFT (0x04) #define RCC_PLL1CFGR (*(volatile uint32_t *)(RCC_BASE + 0x28)) /* RM0456 - Table 108 */ -#define RCC_PLL1CFGR_PLL1REN (1 << 18) -#define RCC_PLL1CFGR_PLL1QEN (1 << 17) -#define RCC_PLL1CFGR_PLL1PEN (1 << 16) -#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) +#define RCC_PLL1CFGR_PLL1REN (1UL << 18) +#define RCC_PLL1CFGR_PLL1QEN (1UL << 17) +#define RCC_PLL1CFGR_PLL1PEN (1UL << 16) +#define RCC_PLL1CFGR_PLL1FRACEN (1UL << 4) #define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) #define RCC_PLL1VCIRANGE_1 0x03 #define RCC_PLL1CFGR_PLLM_SHIFT (8) #define RCC_PLL1CFGR_PLL1MBOOST_SHIFT (12) -#define RCC_PLL1CFGR_PLL1MBOOST_DIV4 0x02 +#define RCC_PLL1CFGR_PLL1MBOOST_DIV4 0x02UL -#define RCC_PLLCKSELR_PLLSRC_NONE 0x0 -#define RCC_PLLCKSELR_PLLSRC_MSI 0x1 -#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2 -#define RCC_PLLCKSELR_PLLSRC_HSE 0x3 +#define RCC_PLLCKSELR_PLLSRC_NONE 0x0UL +#define RCC_PLLCKSELR_PLLSRC_MSI 0x1UL +#define RCC_PLLCKSELR_PLLSRC_HSI16 0x2UL +#define RCC_PLLCKSELR_PLLSRC_HSE 0x3UL #define RCC_PLL1DIVR (*(volatile uint32_t *)(RCC_BASE + 0x34)) /* RM0456 - Table 108 */ @@ -107,36 +107,36 @@ #define RCC_CIER (*(volatile uint32_t *)(RCC_BASE + 0x50)) /* RM0456 - Table 108 */ #define RCC_AHB1ENR (*(volatile uint32_t *)(RCC_BASE + 0x88)) /* RM0456 - Table 108 */ -#define RCC_AHB1ENR_GTZC1EN (1 << 24) +#define RCC_AHB1ENR_GTZC1EN (1UL << 24) #define RCC_AHB3ENR (*(volatile uint32_t *)(RCC_BASE + 0x94)) /* RM0456 - Table 108 */ -#define RCC_AHB3ENR_GTZC2EN (1 << 12) -#define RCC_AHB3ENR_PWREN (1 << 2) +#define RCC_AHB3ENR_GTZC2EN (1UL << 12) +#define RCC_AHB3ENR_PWREN (1UL << 2) #define RCC_ICSCR1 (*(volatile uint32_t *)(RCC_BASE + 0x08)) #define RCC_ICSCR1_MSIRANGE_SHIFT (28) -#define RCC_ICSCR1_MSIRGSEL (1 << 23) +#define RCC_ICSCR1_MSIRGSEL (1UL << 23) #define RCC_ICSCR1_MSIRG_0 (0) #define RCC_ICSCR2 (*(volatile uint32_t *)(RCC_BASE + 0x0C)) #define RCC_ICSCR2_MSITRIM0_SHIFT (15) -#define RCC_ICSCR2_MSITRIM0_DEFAULT (0x10) +#define RCC_ICSCR2_MSITRIM0_DEFAULT (0x10UL) #define RCC_ICSCR3 (*(volatile uint32_t *)(RCC_BASE + 0x10)) #define RCC_ICSCR3_HSITRIM_SHIFT (16) -#define RCC_ICSCR3_HSITRIM_DEFAULT (0x10) +#define RCC_ICSCR3_HSITRIM_DEFAULT (0x10UL) /*** PWR ***/ /*!< Memory & Instance aliases and base addresses for Non-Secure peripherals */ #define PWR_BASE (0x46020800) /* RM0456 - Table 4 */ #define PWR_VOSR (*(volatile uint32_t *)(PWR_BASE + 0x0C)) -#define PWR_VOSR_BOOSTEN (1 << 18) +#define PWR_VOSR_BOOSTEN (1UL << 18) #define PWR_VOSR_VOS_SHIFT (16) -#define PWR_VOSR_VOS_4 (0x0) -#define PWR_VOSR_VOS_3 (0x1) -#define PWR_VOSR_VOS_2 (0x2) -#define PWR_VOSR_VOS_1 (0x3) +#define PWR_VOSR_VOS_4 (0x0UL) +#define PWR_VOSR_VOS_3 (0x1UL) +#define PWR_VOSR_VOS_2 (0x2UL) +#define PWR_VOSR_VOS_1 (0x3UL) #define PWR_VOSR_VOSRDY (1 << 15) #define PWR_VOSR_BOOSTRDY (1 << 14) @@ -181,13 +181,13 @@ #define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_OBL_LAUNCH (1 << 27) #define FLASH_CR_INV (1 << 29) -#define FLASH_CR_OPTLOCK (1 << 30) -#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_OPTLOCK (1UL << 30) +#define FLASH_CR_LOCK (1UL << 31) #define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) #define FLASH_ACR_LATENCY_MASK (0x0F) -#define FLASH_ACR_PRFTEN (1<<8) +#define FLASH_ACR_PRFTEN (1UL << 8) #define FLASH_OPTR (*(volatile uint32_t *)(FLASH_BASE + 0x40)) #define FLASH_OPTR_DBANK (1 << 21) @@ -394,7 +394,7 @@ static void clock_pll_on(int powersave) RCC_ICSCR1|= RCC_ICSCR1_MSIRGSEL; reg32 = RCC_ICSCR1; - reg32 &= ~( (0xF << RCC_ICSCR1_MSIRANGE_SHIFT)); + reg32 &= ~( (0xFUL << RCC_ICSCR1_MSIRANGE_SHIFT)); reg32|= (RCC_ICSCR1_MSIRG_0 << RCC_ICSCR1_MSIRANGE_SHIFT); RCC_ICSCR1 = reg32; reg32 = RCC_ICSCR1; @@ -402,7 +402,7 @@ static void clock_pll_on(int powersave) /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ reg32 = RCC_ICSCR2; - reg32 &= ~((0x1F << RCC_ICSCR2_MSITRIM0_SHIFT)); + reg32 &= ~((0x1FUL << RCC_ICSCR2_MSITRIM0_SHIFT)); reg32 |= (RCC_ICSCR2_MSITRIM0_DEFAULT << RCC_ICSCR2_MSITRIM0_SHIFT); RCC_ICSCR2 = reg32; reg32 = RCC_ICSCR2; diff --git a/hal/stm32wb.c b/hal/stm32wb.c index c7ad0db51..5a2a58b61 100644 --- a/hal/stm32wb.c +++ b/hal/stm32wb.c @@ -94,31 +94,31 @@ PKA_HandleTypeDef hpka = { }; #define FLASH_PAGE_SIZE (0x1000) /* 4KB */ /* Register values */ -#define FLASH_ACR_LATENCY_MASK (0x07) +#define FLASH_ACR_LATENCY_MASK (0x07UL) #ifndef WOLFSSL_STM32_PKA -#define FLASH_SR_BSY (1 << 16) -#define FLASH_SR_CFGBSY (1 << 18) -#define FLASH_SR_SIZERR (1 << 6) -#define FLASH_SR_PGAERR (1 << 5) -#define FLASH_SR_WRPERR (1 << 4) -#define FLASH_SR_PROGERR (1 << 3) -#define FLASH_SR_EOP (1 << 0) +#define FLASH_SR_BSY (1UL << 16) +#define FLASH_SR_CFGBSY (1UL << 18) +#define FLASH_SR_SIZERR (1UL << 6) +#define FLASH_SR_PGAERR (1UL << 5) +#define FLASH_SR_WRPERR (1UL << 4) +#define FLASH_SR_PROGERR (1UL << 3) +#define FLASH_SR_EOP (1UL << 0) -#define FLASH_CR_LOCK (1 << 31) -#define FLASH_CR_STRT (1 << 16) +#define FLASH_CR_LOCK (1UL << 31) +#define FLASH_CR_STRT (1UL << 16) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_PG (1 << 0) -#define FLASH_CR_FSTPG (1 << 18) +#define FLASH_CR_PER (1UL << 1) +#define FLASH_CR_PG (1UL << 0) +#define FLASH_CR_FSTPG (1UL << 18) #endif /* !WOLFSSL_STM32_PKA */ #define FLASH_CR_PNB_SHIFT 3 -#define FLASH_CR_PNB_MASK 0xFF +#define FLASH_CR_PNB_MASK 0xFFUL -#define FLASH_KEY1 (0x45670123) -#define FLASH_KEY2 (0xCDEF89AB) +#define FLASH_KEY1 (0x45670123UL) +#define FLASH_KEY2 (0xCDEF89ABUL) static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates) diff --git a/hal/uart/uart_drv_stm32wb.c b/hal/uart/uart_drv_stm32wb.c index bcb3bf805..146726d53 100644 --- a/hal/uart/uart_drv_stm32wb.c +++ b/hal/uart/uart_drv_stm32wb.c @@ -67,15 +67,15 @@ static void uart_pins_setup(void) uint32_t reg; AHB2_CLOCK_ER |= GPIOB_AHB2_CLOCK_ER; /* Set mode = AF */ - reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2)); + reg = GPIOB_MODE & ~ (0x03UL << (UART1_RX_PIN * 2)); GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2)); - reg = GPIOB_MODE & ~ (0x03 << (UART1_TX_PIN * 2)); + reg = GPIOB_MODE & ~ (0x03UL << (UART1_TX_PIN * 2)); GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2)); /* Alternate function: use low pins (6 and 7) */ - reg = GPIOB_AFL & ~(0xf << ((UART1_TX_PIN) * 4)); + reg = GPIOB_AFL & ~(0xfUL << ((UART1_TX_PIN) * 4)); GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4)); - reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4)); + reg = GPIOB_AFL & ~(0xfUL << ((UART1_RX_PIN) * 4)); GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4)); } diff --git a/src/pci.c b/src/pci.c index 7ff6e671d..3dff773c7 100644 --- a/src/pci.c +++ b/src/pci.c @@ -202,7 +202,7 @@ static void pci_ecam_config_write16(uint8_t bus, uint8_t dev, uint8_t fun, #define PCI_IO_CONFIG_ADDR(bus, dev, fn, off) \ (uint32_t)( \ - (1 << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \ + (1UL << PCI_CONFIG_ADDRESS_ENABLE_BIT_SHIFT) | \ (bus << PCI_CONFIG_ADDRESS_BUS_SHIFT) | \ (dev << PCI_CONFIG_ADDRESS_DEVICE_SHIFT) | \ (fn << PCI_CONFIG_ADDRESS_FUNCTION_SHIFT) | \