Add quizzes to required sections for issue CircuitVerse#617

docs/seq-msi/counters.md

@@ -138,3 +138,30 @@ The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle
 |**After 2nd negative clock edge**|On the arrival of second negative clock edge, FF-A toggles again and QA changes from 1 to 0.But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB changes from 0 to 1.QBQA = 10 after the second clock pulse.|
 |**After 3rd negative clock edge**|On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B.QBQA = 11 after the third clock pulse.|
 |**After 4th negative clock edge**|On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0.QBQA = 00 after the fourth clock pulse.|
+{:.quiz}
+
+What is the primary function of an up-counter?
+
+To increment a binary number with each clock cycle
+To decrement a binary number with each clock cycle
+To store a binary number
+What is the primary function of a down-counter?
+
+To decrement a binary number with each clock cycle
+To increment a binary number with each clock cycle
+To store a binary number
+What type of counter changes its output state on the falling edge of the clock signal?
+
+Negative edge-triggered counter
+Positive edge-triggered counter
+Asynchronous counter
+In a synchronous counter, which type of flip-flops are used?
+
+D flip-flops
+SR flip-flops
+JK flip-flops
+What type of counter has its output state change asynchronously with the input clock signal?
+
+Asynchronous (Ripple) counter
+Synchronous counter
+Decade counter

docs/seq-msi/registers.md

@@ -226,3 +226,30 @@ The initial status of the D flip-flops in the absence of the clock signal is Q2Q
 Similarly, the following operations take place for every positive edge of the clock signal.
 - Serial input of first D flip-flop gets the previous complemented output of the third flip-flop. So, the present output of the first D flip-flop is equal to the previous complemented output of the third flip-flop.
 - The previous outputs of first and second D flip-flops are right shifted by one bit. That means, the present outputs of second and third D flip-flops are equal to the previous outputs of first and second D flip-flops.
+{:.quiz}
+
+What is the primary function of a flip-flop within a register?
+
+To provide temporary storage of a single bit
+To convert analog signals to digital signals
+To perform arithmetic operations on data
+Which type of register is used for performing arithmetic and logic operations in a processor?
+
+Accumulator register
+Data register
+Address register
+Which register is responsible for holding the memory address of the next instruction to be executed in a CPU?
+
+Program Counter (PC)
+Stack Pointer (SP)
+Instruction Register (IR)
+What is the primary difference between a shift register and a counter?
+
+A shift register moves data within a fixed number of stages, while a counter accumulates a count value
+A shift register calculates the sum of all individual resistances, while a counter calculates the product of individual resistances
+A shift register stores data temporarily, while a counter amplifies signals
+In a microcontroller, which register is used to store the result of an input/output operation?
+
+Input-Output Data Register (IODR)
+General-Purpose Register (GPR)
+Status Register (SR)

docs/seq-ssi/clock-signals.md

@@ -73,3 +73,30 @@ If the sequential circuit is operated with the clock signal that is transitionin
 If the sequential circuit is operated with the clock signal that is transitioning from Logic High to Logic Low, then that type of triggering is known as **Negative edge triggering**. It is also called as **falling edge triggering**. It is shown in the following figure.
 
 {% include image.html url="/assets/images/negative_edge_triggering.jpg" description="" %}
+{:.quiz}
+
+What is the unit of frequency for a clock signal?
+
+Hertz (Hz)
+Seconds
+Ohms
+What is the term used to describe the time between two consecutive rising edges of a clock signal?
+
+Period
+Frequency
+Duty cycle
+What is the term used to describe the ratio of the time the clock signal is high to the total time of one cycle?
+
+Duty cycle
+Frequency
+Period
+What type of oscillator circuit generates a stable clock signal in digital circuits?
+
+Crystal oscillator
+RC oscillator
+LC oscillator
+What is the term used to describe the maximum rate at which a clock signal can change from one state to another?
+
+Clock speed
+Frequency
+Duty cycle

docs/seq-ssi/flip-flops.md

@@ -285,3 +285,32 @@ Q(n+1) = Q(n)'J + Q(n)K'
 ## Flip-flops interaction
 
 {% include flipflop2.html %}
+{:.quiz}
+
+What type of flip-flop can be used to eliminate the race-around condition in JK flip-flops?
+
+Master-slave flip-flop
+Edge-triggered flip-flop
+D flip-flop
+Which type of flip-flop stores a single bit of data and has a clock input?
+
+D flip-flop
+SR flip-flop
+JK flip-flop
+In an SR flip-flop, what happens when both S and R inputs are set to 1?
+
+Invalid state or undefined behavior
+The output remains unchanged
+The output is set to 1
+Which type of flip-flop has two stable states and can be toggled between them with a single input?
+
+T flip-flop
+D flip-flop
+SR flip-flop
+What type of flip-flop is commonly used in shift registers and counters?
+
+D flip-flop
+SR flip-flop
+T flip-flop
+
+