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Merge branch 'isa_fix_network_module_uvm' into 'devel'
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Style change in network module verification

See merge request ndk/ndk-fpga!134
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@jakubcabal
jakubcabal committed Jan 9, 2025
2 parents 5c09cf4 + 91ecd30 commit 8bf1211
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Showing 11 changed files with 105 additions and 172 deletions.
5 changes: 4 additions & 1 deletion comp/nic/mac_lite/tx_mac_lite/tx_mac_lite.vhd
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Expand Up @@ -819,7 +819,10 @@ begin

assert (tx_gap_inside_frame_dbg_reg /= '1')
report "TX_MAC_LITE: Gap inside frame on TX MFB stream!"
severity failure;
severity warning;
--change severity to warning, because questa sim have problem with this assert and
--evaluate it wrongly
--severity failure;

-- =========================================================================
-- STATISTICS MODULE
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3 changes: 0 additions & 3 deletions core/comp/eth/network_mod/comp/network_mod_core/Modules.tcl
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Expand Up @@ -98,9 +98,6 @@ if { $ARCHGRP == "F_TILE"} {
lappend MOD "$ENTITY_BASE/comps/ftile/ftile_multirate_eth_2x100g4.vhd"
lappend MOD "$ENTITY_BASE/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd"

# Verification probe
lappend MOD "$ENTITY_BASE/comps/ftile_ver_probe/ftile_ver_probe.vhd"

lappend MOD "$ENTITY_BASE/network_mod_core_ftile.vhd"
}

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76 changes: 0 additions & 76 deletions core/comp/eth/network_mod/comp/network_mod_core/comps/ftile_ver_probe/ftile_ver_probe.vhd
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This file was deleted.

51 changes: 7 additions & 44 deletions core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ftile.vhd
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Expand Up @@ -204,15 +204,6 @@ architecture FULL of NETWORK_MOD_CORE is
signal ftile_rx_mac_error : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_ERROR_WIDTH -1 downto 0);
signal ftile_rx_mac_status : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_STATUS_WIDTH -1 downto 0);

-- Verification probe signals
signal ver_probe_ftile_rx_mac_data : slv_array_t (ETH_PORT_CHAN-1 downto 0)(MAC_DATA_WIDTH -1 downto 0);
signal ver_probe_ftile_rx_mac_valid : std_logic_vector(ETH_PORT_CHAN-1 downto 0);
signal ver_probe_ftile_rx_mac_inframe : slv_array_t (ETH_PORT_CHAN-1 downto 0)(MAC_INFRAME_WIDTH -1 downto 0);
signal ver_probe_ftile_rx_mac_eop_empty : slv_array_t (ETH_PORT_CHAN-1 downto 0)(MAC_EOP_EMPTY_WIDTH -1 downto 0);
signal ver_probe_ftile_rx_mac_fcs_error : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_FCS_ERROR_WIDTH-1 downto 0);
signal ver_probe_ftile_rx_mac_error : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_ERROR_WIDTH -1 downto 0);
signal ver_probe_ftile_rx_mac_status : slv_array_t (ETH_PORT_CHAN-1 downto 0)(RX_MAC_STATUS_WIDTH -1 downto 0);

begin

mi_splitter_i : entity work.MI_SPLITTER_PLUS_GEN
Expand Down Expand Up @@ -766,34 +757,6 @@ architecture FULL of NETWORK_MOD_CORE is
end generate;
end generate ftile_8x10g1_g;

verification_probe_i : entity work.NETWORK_MOD_CORE_FTILE_VER_PROBE
generic map(
CHANNELS => ETH_PORT_CHAN,
DATA_WIDTH => MAC_DATA_WIDTH,
INFRAME_WIDTH => MAC_INFRAME_WIDTH,
EOP_EMPTY_WIDTH => MAC_EOP_EMPTY_WIDTH,
FCS_ERROR_WIDTH => RX_MAC_FCS_ERROR_WIDTH,
ERROR_WIDTH => RX_MAC_ERROR_WIDTH,
STATUS_WIDTH => RX_MAC_STATUS_WIDTH
)
port map(
IN_MAC_DATA => ftile_rx_mac_data,
IN_MAC_INFRAME => ftile_rx_mac_inframe,
IN_MAC_EOP_EMPTY => ftile_rx_mac_eop_empty,
IN_MAC_FCS_ERROR => ftile_rx_mac_fcs_error,
IN_MAC_ERROR => ftile_rx_mac_error,
IN_MAC_STATUS => ftile_rx_mac_status,
IN_MAC_VALID => ftile_rx_mac_valid,

OUT_MAC_DATA => ver_probe_ftile_rx_mac_data,
OUT_MAC_INFRAME => ver_probe_ftile_rx_mac_inframe,
OUT_MAC_EOP_EMPTY => ver_probe_ftile_rx_mac_eop_empty,
OUT_MAC_FCS_ERROR => ver_probe_ftile_rx_mac_fcs_error,
OUT_MAC_ERROR => ver_probe_ftile_rx_mac_error,
OUT_MAC_STATUS => ver_probe_ftile_rx_mac_status,
OUT_MAC_VALID => ver_probe_ftile_rx_mac_valid
);

adapts_g : for i in ETH_PORT_CHAN-1 downto 0 generate
-- =========================================================================
-- ADAPTERS
Expand All @@ -806,13 +769,13 @@ architecture FULL of NETWORK_MOD_CORE is
port map(
CLK => ftile_clk_out,
RESET => RESET_ETH,
IN_MAC_DATA => ver_probe_ftile_rx_mac_data(i),
IN_MAC_INFRAME => ver_probe_ftile_rx_mac_inframe(i),
IN_MAC_EOP_EMPTY => ver_probe_ftile_rx_mac_eop_empty(i),
IN_MAC_FCS_ERROR => ver_probe_ftile_rx_mac_fcs_error(i),
IN_MAC_ERROR => ver_probe_ftile_rx_mac_error(i),
IN_MAC_STATUS => ver_probe_ftile_rx_mac_status(i),
IN_MAC_VALID => ver_probe_ftile_rx_mac_valid(i),
IN_MAC_DATA => ftile_rx_mac_data(i),
IN_MAC_INFRAME => ftile_rx_mac_inframe(i),
IN_MAC_EOP_EMPTY => ftile_rx_mac_eop_empty(i),
IN_MAC_FCS_ERROR => ftile_rx_mac_fcs_error(i),
IN_MAC_ERROR => ftile_rx_mac_error(i),
IN_MAC_STATUS => ftile_rx_mac_status(i),
IN_MAC_VALID => ftile_rx_mac_valid(i),
OUT_MFB_DATA => TX_MFB_DATA(i),
OUT_MFB_ERROR => TX_MFB_ERROR(i),
OUT_MFB_SOF => TX_MFB_SOF(i),
Expand Down
3 changes: 2 additions & 1 deletion core/comp/eth/network_mod/uvm/tbench/base/dut.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ module DUT_BASE #(
string DEVICE,
string BOARD
)(
output wire logic CLK_ETH[ETH_PORTS],
input wire logic CLK_USR,
input wire logic CLK_MI,
input wire logic CLK_MI_PHY,
Expand Down Expand Up @@ -158,7 +159,7 @@ module DUT_BASE #(
)
VHDL_DUT_U (
.CLK_USER (CLK_USR),
.CLK_ETH (),
.CLK_ETH (CLK_ETH),

.RESET_USER (reset_user),
.RESET_ETH (reset_eth),
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11 changes: 8 additions & 3 deletions core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv
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Expand Up @@ -40,9 +40,10 @@ module DUT #(
int unsigned RESET_WIDTH,

string DEVICE,
string BOARD
string BOARD,
time CLK_ETH_PERIOD[ETH_PORTS]
)(
input wire logic CLK_ETH[ETH_PORTS],
output wire logic CLK_ETH[ETH_PORTS],
input wire logic CLK_USR,
input wire logic CLK_MI,
input wire logic CLK_MI_PHY,
Expand Down Expand Up @@ -97,6 +98,7 @@ module DUT #(
.DEVICE (DEVICE ),
.BOARD (BOARD )
) DUT_BASE_U (
.CLK_ETH (CLK_ETH ),
.CLK_USR (CLK_USR ),
.CLK_MI (CLK_MI ),
.CLK_MI_PHY (CLK_MI_PHY),
Expand Down Expand Up @@ -127,6 +129,9 @@ module DUT #(
initial assert(ETH_PORT_CHAN_LOCAL == 1);

wire logic [4*128-1 : 0] eth_rx_data;
logic CLK_ETH_GEN = 1'b0;

always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN;

// ------- //
// TX side //
Expand Down Expand Up @@ -173,7 +178,7 @@ module DUT #(
// ----- //

// CLK connection
initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH[eth_it];
initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH_GEN;
end
endgenerate

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5 changes: 3 additions & 2 deletions core/comp/eth/network_mod/uvm/tbench/cmac/testbench.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ module testbench;
// ------ //

logic CLK_USR = 0;
logic CLK_ETH[ETH_PORTS] = '{ETH_PORTS{1'b0}};
logic CLK_ETH[ETH_PORTS];
logic CLK_MI = 0;
logic CLK_MI_PHY = 0;
logic CLK_MI_PMD = 0;
Expand Down Expand Up @@ -168,7 +168,8 @@ module testbench;
.LANE_TX_POLARITY (LANE_TX_POLARITY ),
.RESET_WIDTH (RESET_WIDTH ),
.DEVICE (DEVICE ),
.BOARD (BOARD )
.BOARD (BOARD ),
.CLK_ETH_PERIOD (CLK_ETH_PERIOD )
) DUT_U (
.CLK_ETH (CLK_ETH ),
.CLK_USR (CLK_USR ),
Expand Down
10 changes: 7 additions & 3 deletions core/comp/eth/network_mod/uvm/tbench/e-tile/dut.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -40,9 +40,10 @@ module DUT #(
int unsigned RESET_WIDTH,

string DEVICE,
string BOARD
string BOARD,
time CLK_ETH_PERIOD[ETH_PORTS]
)(
input wire logic CLK_ETH[ETH_PORTS],
output wire logic CLK_ETH[ETH_PORTS],
input wire logic CLK_USR,
input wire logic CLK_MI,
input wire logic CLK_MI_PHY,
Expand Down Expand Up @@ -99,6 +100,7 @@ module DUT #(
.DEVICE (DEVICE ),
.BOARD (BOARD )
) DUT_BASE_U (
.CLK_ETH (CLK_ETH ),
.CLK_USR (CLK_USR ),
.CLK_MI (CLK_MI ),
.CLK_MI_PHY (CLK_MI_PHY),
Expand Down Expand Up @@ -126,7 +128,9 @@ module DUT #(
generate;
for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin
logic [AVST_WIDTH*ITEM_WIDTH-1 : 0] avst_data;
logic CLK_ETH_GEN = 1'b0;

always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN;
// RX
for (genvar data_it = 0; data_it < AVST_WIDTH; data_it++) begin
assign avst_data[(AVST_WIDTH -data_it)*ITEM_WIDTH-1 -: ITEM_WIDTH] = eth_rx[eth_it].DATA[(data_it+1)*ITEM_WIDTH-1 -: ITEM_WIDTH];
Expand All @@ -152,7 +156,7 @@ module DUT #(
assign DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.tx_avst_ready[0] = eth_tx[eth_it].READY;

// CLK
assign DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.etile_clk_out_vec[0] = CLK_ETH[eth_it];
assign DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.etile_clk_out_vec[0] = CLK_ETH_GEN;
end
endgenerate

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5 changes: 3 additions & 2 deletions core/comp/eth/network_mod/uvm/tbench/e-tile/testbench.sv
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Expand Up @@ -21,7 +21,7 @@ module testbench;
// -------------------------------------------------------------------------------------------------------------------------------------------------------------------
// CLOCK
logic CLK_USR = 0;
logic CLK_ETH[ETH_PORTS] = '{ETH_PORTS{1'b0}};
logic CLK_ETH[ETH_PORTS];
logic CLK_MI = 0;
logic CLK_MI_PHY = 0;
logic CLK_MI_PMD = 0;
Expand Down Expand Up @@ -156,7 +156,8 @@ module testbench;
.LANE_TX_POLARITY (LANE_TX_POLARITY ),
.RESET_WIDTH (RESET_WIDTH ),
.DEVICE (DEVICE ),
.BOARD (BOARD )
.BOARD (BOARD ),
.CLK_ETH_PERIOD (CLK_ETH_PERIOD )
) DUT_U (
.CLK_ETH (CLK_ETH ),
.CLK_USR (CLK_USR ),
Expand Down
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