Finalize GSoD2020

_sass/custom/custom.scss

@@ -333,3 +333,8 @@ $text-color: #111111;
     padding: 0.5rem;
   }
 }
+
+// Disqus Recommendations
+#disqus_recommendations {
+  margin-top: 20px;
+}

docs/comb-lsi/plds.md

@@ -5,6 +5,7 @@ nav_order: l1s000
 cvib_level: medium
 parent: Combinational LSI
 has_children: false
+published: false
 ---
 
 # Programmable Logic Devices

docs/comb-ssi/symbols.md

@@ -5,6 +5,7 @@ nav_order: l0s000
 cvib_level: basic
 parent: Combinational SSI
 has_children: false
+published: false
 ---
 
 # Symbols

docs/comb-ssi/time-behaviour.md

@@ -5,6 +5,7 @@ nav_order: l2s000
 cvib_level: advanced
 parent: Combinational SSI
 has_children: false
+published: false
 ---
 
 # Time behaviour

docs/comb-ssi/truth-tables.md

@@ -5,6 +5,7 @@ nav_order: l0s002
 cvib_level: basic
 parent: Combinational SSI
 has_children: false
+published: false
 ---
 
 # Truth tables

docs/seq-lsi/fpga.md

@@ -21,7 +21,7 @@ has_children: false
 
 ## Introduction
 
-In 1985, a new programmable hardware architecture evolved from the [PLDs]({% link docs/comb-lsi/plds.md %}), the *Field Programmable Gate Array* (FPGA) developed by Xilix Inc. See the IEEE Chip Hall of Fame entry on the [Xilinx XC2064 FPGA](https://spectrum.ieee.org/tech-history/silicon-revolution/chip-hall-of-fame-xilinx-xc2064-fpga) for some history about it.
+In 1985, a new programmable hardware architecture evolved from the PLDs {% comment %}[PLDs]({% link docs/comb-lsi/plds.md %}){% endcomment %}, the *Field Programmable Gate Array* (FPGA) developed by Xilix Inc. See the IEEE Chip Hall of Fame entry on the [Xilinx XC2064 FPGA](https://spectrum.ieee.org/tech-history/silicon-revolution/chip-hall-of-fame-xilinx-xc2064-fpga) for some history about it.
 
 An FPGA chip contains several *logic cells* which can be arbitrarily interconnected according to the programmed configuration.
 

docs/seq-ssi/asynchronous-systems.md

@@ -5,6 +5,7 @@ nav_order: l1s002
 cvib_level: medium
 parent: Sequential SSI
 has_children: false
+published: false
 ---
 
 # Asynchronous systems

docs/seq-ssi/synchronous-systems.md

@@ -5,6 +5,7 @@ nav_order: l1s001
 cvib_level: medium
 parent: Sequential SSI
 has_children: false
+published: false
 ---
 
 # Synchronous systems

docs/seq-ssi/time-diagrams.md

@@ -5,6 +5,7 @@ nav_order: l0s003
 cvib_level: basic
 parent: Sequential SSI
 has_children: false
+published: false
 ---
 
 # Time diagrams