Added quizes for flip-flop,clock-signals,counters and register

docs/comb-msi/mux-demux.md

@@ -180,21 +180,18 @@ A 1 : 16 demultiplexer can be implemented using **two** 1 : 8 demultiplexers.
    *  Both MUX & DEMUX
 
 2. Which of the following logic block has a number of input lines and one signle output line ?
-
    * Decoder
    1. Multiplexer
    * Demultiplexer
    * Encoder
 
 3. How many selection line will be there if a multiplexer has 8 input lines ?
-
    * 1
    * 2
    1. 3
    * 4
 
 4. How many output lines will be there in a demultiplexer if it has 3 selection lines ?
-
    1. 1
    * 2
    * 3

docs/logic-design/binary-cubes.md

@@ -71,6 +71,6 @@ The adjacency is key to group cubes in Karnaugh maps and in the Quine McCluskey
    * Circle
    * Triangle
 3. Which shape is represented by an object having exactly 3 variables?
-      1. Cube
-      * Parallelogram
-      * Sphere
+   1. Cube
+   * Parallelogram
+   * Sphere

docs/logic-design/kmaps.md

@@ -190,21 +190,19 @@ This illustrates the idea that this is a greedy algorithm, and does not always r
 {:.quiz}
 
 1. ___  are known as diagonal mapping ?
-	* POS
-	* SOP
-	1. Entries
-        * Latches
+    * POS
+    * SOP
+    1. Entries
+    * Latches
 
 2. K-map can be used to minimize functions of up to ___ variables ?
-	* 5
-	* 2
-	1. 6
-	*  3
+    * 5
+    * 2
+    1. 6
+    *  3
 
 3. In which K-map 16 cells are there ?
-        * 2-variable
-	* 3-variable
-	1. 4-variable
-	* 5-variable
-
-
+    * 2-variable
+    * 3-variable
+    1. 4-variable
+    * 5-variable

docs/seq-msi/counters.md

@@ -138,3 +138,35 @@ The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle
 |**After 2nd negative clock edge**|On the arrival of second negative clock edge, FF-A toggles again and QA changes from 1 to 0.But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB changes from 0 to 1.QBQA = 10 after the second clock pulse.|
 |**After 3rd negative clock edge**|On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B.QBQA = 11 after the third clock pulse.|
 |**After 4th negative clock edge**|On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0.QBQA = 00 after the fourth clock pulse.|
+
+{:.quiz}
+
+1. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
+    * 0 to 2n
+    * 0 to 2n + 1
+    * 0 to 2n+1/2
+    1. 0 to 2n – 1
+
+2. A decimal counter has ______ states.
+    * 5
+    1. 10
+    * 18
+    * 20
+
+3. Three decade counter would have _____BCD counter.
+    * 2
+    * 4
+    1. 3
+    * 5
+
+4. The expression for MOD number for a ripple counter with N flip-flops is
+    1. 2^N
+    * N^2
+    * 2^(N-1)
+    * 2^N -1
+
+5. A ripple counter with n flip-flops can function as a
+    * n: 1 counter
+    * n/2: 1 counter
+    * 2n: 1 counter
+    1. 2^N: 1 counter

docs/seq-msi/registers.md

@@ -226,3 +226,33 @@ The initial status of the D flip-flops in the absence of the clock signal is Q2Q
 Similarly, the following operations take place for every positive edge of the clock signal.
 - Serial input of first D flip-flop gets the previous complemented output of the third flip-flop. So, the present output of the first D flip-flop is equal to the previous complemented output of the third flip-flop.
 - The previous outputs of first and second D flip-flops are right shifted by one bit. That means, the present outputs of second and third D flip-flops are equal to the previous outputs of first and second D flip-flops.
+
+{:.quiz}
+
+1. The register is a type of ___________
+     1. Sequential circuit
+     * Combinational circui
+     * CPU
+     * Latches
+
+2. In serial shifting method, data shifting occurs ____________
+     * simultaneously
+     * Two bits at a time
+     * Four bits at a time
+     1. One bit at a time
+
+3. A register that is used to store binary information is called ___________
+     * Data register
+     * Shift register
+     1. Binary register
+     * D – Register
+
+4. How many flip-flops are used in the register when storage bit capacity is 6?
+     * 3
+     * 4
+     * 2
+     1. 6
+
+5. When the flip-flops are connected in such a way that the output of every flip-flop is connected with the input of another flip-flop is called Cascade.
+     1. True
+     * False

docs/seq-ssi/clock-signals.md

@@ -73,3 +73,29 @@ If the sequential circuit is operated with the clock signal that is transitionin
 If the sequential circuit is operated with the clock signal that is transitioning from Logic High to Logic Low, then that type of triggering is known as **Negative edge triggering**. It is also called as **falling edge triggering**. It is shown in the following figure.
 
 {% include image.html url="/assets/images/negative_edge_triggering.jpg" description="" %}
+
+{:.quiz}
+
+1. What must be used along with synchronous control inputs to trigger a change in the flip-flop?
+    * 0
+    * 1
+    1. clock
+    * previous output
+
+2. What gate is placed between clock input and the input of AND gate to convert a positive level triggered flip – flop to a negative level triggered flip – flop?
+    * NOT gate
+    1. NOR gate
+    * Buffer
+    * NAND gate
+
+3. The flip-flop is only activated by _____________
+    * +ve edge trigger
+    * -ve edge trigger
+    1. both +ve and -ve
+    * None of the above
+
+4. How many stable states combinational circuits have?
+    * 3
+    * 4
+    * 5
+    1. 2

docs/seq-ssi/flip-flops.md

@@ -285,3 +285,35 @@ Q(n+1) = Q(n)'J + Q(n)K'
 ## Flip-flops interaction
 
 {% include flipflop2.html %}
+
+{:.quiz}
+
+1. How many flip-flops are required to build a binary counter circuit to count from 0 to 1023?
+    * 1
+    * 6
+    1. 10
+    * 23
+
+2. We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is _______.
+    1. 4
+    * 2
+    * 5
+    * 1
+
+3. What is the required flip flop in T to D flip flop conversion?
+    * T flip flop
+    * S-R flip flop
+    1. D flip flop
+    * None of the above
+
+4. The outputs Q and Q̅ of the master-slave SR flip-flop are connected to its R and S inputs respectively. The output Q when clock pulses are applied will be:
+    * Permanently 0
+    * Permanently 1
+    * fixed 0 or 1
+    1. None of the above
+
+5. If input to T flip flop is 200 Hz signal, then what will be the output signal frequency if four T flip flops are connected in cascade
+    * 50 Hz
+    * 800 Hz
+    1. None of the above
+    * 200 Hz