mock-array: run power.tcl from openroad and sta and diff

Signed-off-by: Øyvind Harboe <[email protected]>

flow/designs/asap7/mock-array/config.mk

@@ -54,7 +54,10 @@ simulate:
 
 .PHONY: power
 power:
+	$(OPENROAD_EXE) -no_init -exit designs/asap7/mock-array/power.tcl
+	mv $(OBJECTS_DIR)/power.rpt $(OBJECTS_DIR)/openroad_power.rpt
 	$(OPENSTA_EXE) -no_init -exit designs/asap7/mock-array/power.tcl
+	diff $(OBJECTS_DIR)/power.rpt $(OBJECTS_DIR)/openroad_power.rpt
 
 # Routing by abutment should be easy, limit iterations
 export DETAILED_ROUTE_END_ITERATION ?= 6

flow/designs/asap7/mock-array/power.tcl

@@ -1,14 +1,28 @@
+source $::env(SCRIPTS_DIR)/util.tcl
+
 foreach libFile $::env(LIB_FILES) {
   if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} {
-    read_liberty $libFile
+    # Do not load the macros as we want to flatten the design
+    # to get timing numbers
+    log_cmd read_liberty $libFile
   }
 }
 
-read_verilog results/asap7/mock-array_Element/base/6_final.v
-read_verilog $::env(RESULTS_DIR)/6_final.v
-read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
+log_cmd read_verilog results/asap7/mock-array_Element/base/6_final.v
+log_cmd read_verilog $::env(RESULTS_DIR)/6_final.v
+log_cmd read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
 
-link_design MockArray
+if {[llength [info procs read_lef]]} {
+  # OpenROAD requires .lef files, OpenSTA doesn't
+  read_lef $::env(TECH_LEF)
+  read_lef $::env(SC_LEF)
+  # if {[env_var_exists_and_non_empty ADDITIONAL_LEFS]} {
+  #   foreach lef $::env(ADDITIONAL_LEFS) {
+  #     read_lef $lef
+  #   }
+  # }
+}
+log_cmd link_design MockArray
 
 read_sdc $::env(RESULTS_DIR)/6_final.sdc
 read_spef $::env(RESULTS_DIR)/6_final.spef
@@ -31,3 +45,4 @@ for {set x 0} {$x < 8} {incr x} {
 
 report_power -instances [get_cells $ces]
 report_power
+report_power > $::env(OBJECTS_DIR)/power.rpt