mock-array: add sta-report-checks and openroad-report-checks targets

Signed-off-by: Øyvind Harboe <[email protected]>

flow/designs/asap7/mock-array/config.mk

@@ -56,6 +56,14 @@ simulate:
 power:
 	$(OPENSTA_EXE) -no_init -exit designs/asap7/mock-array/power.tcl
 
+.PHONY: sta-report-checks
+sta-report-checks:
+	$(OPENSTA_EXE) -no_init -exit designs/asap7/mock-array/sta-report-checks.tcl
+
+.PHONY: openroad-report-checks
+openroad-report-checks:
+	$(UNSET_AND_MAKE) ODB_FILE=$(RESULTS_DIR)/6_final.odb RUN_SCRIPT=$(DESIGN_DIR)/openroad-report-checks.tcl run
+
 # Routing by abutment should be easy, limit iterations
 export DETAILED_ROUTE_END_ITERATION ?= 6
 

flow/designs/asap7/mock-array/load.tcl

@@ -0,0 +1,21 @@
+foreach libFile $::env(LIB_FILES) {
+  if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} {
+    read_liberty $libFile
+  }
+}
+
+read_verilog results/asap7/mock-array_Element/base/6_final.v
+read_verilog $::env(RESULTS_DIR)/6_final.v
+read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
+
+link_design MockArray
+
+read_spef $::env(RESULTS_DIR)/6_final.spef
+for {set x 0} {$x < 8} {incr x} {
+  for {set y 0} {$y < 8} {incr y} {
+    read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef
+  }
+}
+
+read_sdc $::env(DESIGN_DIR)/constraints.sdc
+set_propagated_clock [get_clocks {clock}]

flow/designs/asap7/mock-array/openroad-report-checks.tcl

@@ -0,0 +1,2 @@
+source $::env(SCRIPTS_DIR)/open.tcl
+source $::env(DESIGN_DIR)/report-checks.tcl

flow/designs/asap7/mock-array/power.tcl

@@ -1,22 +1,4 @@
-foreach libFile $::env(LIB_FILES) {
-  if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} {
-    read_liberty $libFile
-  }
-}
-
-read_verilog results/asap7/mock-array_Element/base/6_final.v
-read_verilog $::env(RESULTS_DIR)/6_final.v
-read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
-
-link_design MockArray
-
-read_sdc $::env(RESULTS_DIR)/6_final.sdc
-read_spef $::env(RESULTS_DIR)/6_final.spef
-for {set x 0} {$x < 8} {incr x} {
-  for {set y 0} {$y < 8} {incr y} {
-    read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef
-  }
-}
+source $::env(DESIGN_DIR)/load.tcl
 
 report_parasitic_annotation
 report_power

flow/designs/asap7/mock-array/report-checks.tcl

@@ -0,0 +1,3 @@
+source $::env(SCRIPTS_DIR)/util.tcl
+
+log_cmd report_checks

flow/designs/asap7/mock-array/sta-report-checks.tcl

@@ -0,0 +1,6 @@
+# Using Verilog instead of .lib files for greater
+# detail in report_checks across module hierarchy,
+# even if we're using Element macros
+source $::env(DESIGN_DIR)/load.tcl
+
+source $::env(DESIGN_DIR)/report-checks.tcl