Merge pull request #19 from YosysHQ/main

bump fork for version 0.40

CHANGELOG

@@ -2,9 +2,23 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.39 .. Yosys 0.40-dev
+Yosys 0.40 .. Yosys 0.41-dev
 --------------------------
 
+Yosys 0.39 .. Yosys 0.40
+--------------------------
+ * New commands and options
+    - Added option "-vhdl2019" to "read" and "verific" pass. 
+
+ * Various
+    - Major documentation overhaul.
+    - Added port statistics to "stat" command.
+    - Added new formatting features to cxxrtl backend.
+
+ * Verific support
+    - Added better support for VHDL constants import.
+    - Added support for VHDL 2009.
+
 Yosys 0.38 .. Yosys 0.39
 --------------------------
  * New commands and options

CODEOWNERS

@@ -10,6 +10,7 @@
 
 # PATH (can use glob)          USERNAME(S)
 
+CODEOWNERS                     @nakengelhardt
 passes/cmds/scratchpad.cc      @nakengelhardt
 frontends/rpc/                 @whitequark
 backends/cxxrtl/               @whitequark
@@ -19,7 +20,7 @@ passes/opt/opt_lut.cc          @whitequark
 passes/techmap/abc9*.cc        @eddiehung @Ravenslofty
 backends/aiger/xaiger.cc       @eddiehung
 docs/                          @KrystalDelusion
-
+.github/workflows/*.yml        @mmicko
 
 ## External Contributors
 # Only users with write permission to the repository get review

Makefile

@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.39+149
+YOSYS_VER := 0.40+7
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -158,7 +158,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0033808.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline a1bb025.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #
@@ -629,6 +629,7 @@ $(eval $(call add_include_file,kernel/sigtools.h))
 $(eval $(call add_include_file,kernel/timinginfo.h))
 $(eval $(call add_include_file,kernel/utils.h))
 $(eval $(call add_include_file,kernel/yosys.h))
+$(eval $(call add_include_file,kernel/yosys_common.h))
 $(eval $(call add_include_file,kernel/yw.h))
 $(eval $(call add_include_file,libs/ezsat/ezsat.h))
 $(eval $(call add_include_file,libs/ezsat/ezminisat.h))
@@ -984,16 +985,27 @@ docs/gen_images:
 	$(Q) $(MAKE) -C docs images
 
 DOCS_GUIDELINE_FILES := GettingStarted CodingStyle
-docs/guidelines:
-	$(Q) mkdir -p docs/source/temp
-	$(Q) cp -f $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) docs/source/temp
-
-# many of these will return an error which can be safely ignored, so we prefix
-# the command with a '-'
-DOCS_USAGE_PROGS := yosys yosys-config yosys-filterlib yosys-abc yosys-smtbmc yosys-witness
-docs/usage: $(addprefix docs/source/temp/,$(DOCS_USAGE_PROGS))
-docs/source/temp/%: docs/guidelines
-	-$(Q) ./$(PROGRAM_PREFIX)$* --help > $@ 2>&1
+docs/guidelines docs/source/generated:
+	$(Q) mkdir -p docs/source/generated
+	$(Q) cp -f $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) docs/source/generated
+
+# some commands return an error and print the usage text to stderr
+define DOC_USAGE_STDERR
+docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
+	-$(Q) ./$$< --help 2> $$@
+endef
+DOCS_USAGE_STDERR := yosys-config yosys-filterlib yosys-abc
+$(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage))))
+
+# others print to stdout
+define DOC_USAGE_STDOUT
+docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
+	$(Q) ./$$< --help > $$@
+endef
+DOCS_USAGE_STDOUT := yosys yosys-smtbmc yosys-witness
+$(foreach usage,$(DOCS_USAGE_STDOUT),$(eval $(call DOC_USAGE_STDOUT,$(usage))))
+
+docs/usage: $(addprefix docs/source/generated/,$(DOCS_USAGE_STDOUT) $(DOCS_USAGE_STDERR))
 
 docs/reqs:
 	$(Q) $(MAKE) -C docs reqs

backends/verilog/verilog_backend.cc

@@ -2014,22 +2014,29 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
 
 void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
-	if (simple_lhs) {
+	bool all_chunks_wires = true;
+	for (auto &chunk : left.chunks())
+		if (chunk.is_wire() && reg_wires.count(chunk.wire->name))
+			all_chunks_wires = false;
+	if (!simple_lhs && all_chunks_wires) {
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, left);
+		f << stringf(" = ");
+		dump_sigspec(f, right);
+		f << stringf(";\n");
+	} else {
 		int offset = 0;
 		for (auto &chunk : left.chunks()) {
-			f << stringf("%s" "assign ", indent.c_str());
+			if (chunk.is_wire() && reg_wires.count(chunk.wire->name))
+				f << stringf("%s" "always%s\n%s  ", indent.c_str(), systemverilog ? "_comb" : " @*", indent.c_str());
+			else
+				f << stringf("%s" "assign ", indent.c_str());
 			dump_sigspec(f, chunk);
 			f << stringf(" = ");
 			dump_sigspec(f, right.extract(offset, GetSize(chunk)));
 			f << stringf(";\n");
 			offset += GetSize(chunk);
 		}
-	} else {
-		f << stringf("%s" "assign ", indent.c_str());
-		dump_sigspec(f, left);
-		f << stringf(" = ");
-		dump_sigspec(f, right);
-		f << stringf(";\n");
 	}
 }
 

docs/.gitignore

@@ -1,6 +1,6 @@
 /build/
 /source/cmd
-/source/temp
+/source/generated
 /source/_images/**/*.log
 /source/_images/**/*.aux
 /source/_images/**/*.pdf

docs/Makefile

@@ -48,6 +48,7 @@ help:
 clean: clean-examples
 	rm -rf $(BUILDDIR)/*
 	rm -rf source/cmd util/__pycache__
+	rm -rf source/generated
 	$(MAKE) -C source/_images clean
 
 .PHONY: html

docs/source/appendix/auxprogs.rst

@@ -11,7 +11,7 @@ The ``yosys-config`` tool (an auto-generated shell-script) can be used to query
 compiler options and other information needed for building loadable modules for
 Yosys. See :doc:`/yosys_internals/extending_yosys/extensions` for details.
 
-.. literalinclude:: /temp/yosys-config
+.. literalinclude:: /generated/yosys-config
     :start-at: Usage
 
 .. _sec:filterlib:
@@ -25,7 +25,7 @@ The ``yosys-filterlib`` tool is a small utility that can be used to strip or
 extract information from a Liberty file.  This can be useful for removing
 sensitive or proprietary information such as timing or other trade secrets.
 
-.. literalinclude:: /temp/yosys-filterlib
+.. literalinclude:: /generated/yosys-filterlib
     :start-at: Usage
 
 yosys-abc
@@ -36,17 +36,16 @@ been accepted upstream. Not all versions of Yosys work with all versions of ABC.
 So Yosys comes with its own yosys-abc to avoid compatibility issues between the
 two.
 
-.. literalinclude:: /temp/yosys-abc
+.. literalinclude:: /generated/yosys-abc
     :start-at: usage
-    :end-before: UC Berkeley
 
 yosys-smtbmc
 ------------
 
 The ``yosys-smtbmc`` tool is a utility used by SBY for interacting with smt
 solvers.
 
-.. literalinclude:: /temp/yosys-smtbmc
+.. literalinclude:: /generated/yosys-smtbmc
 
 yosys-witness
 -------------
@@ -55,7 +54,7 @@ yosys-witness
 This is used in SBY and SCY for producing traces in a consistent format
 independent of the solver.
 
-.. literalinclude:: /temp/yosys-witness
+.. literalinclude:: /generated/yosys-witness
     :start-at: Usage
 
 .. note:: ``yosys-witness`` requires `click`_ Python package for use.

docs/source/cmd_ref.rst

@@ -4,7 +4,7 @@
 Command line reference
 ================================================================================
 
-.. literalinclude:: /temp/yosys
+.. literalinclude:: /generated/yosys
     :start-at: Usage
 
 .. toctree::

docs/source/code_examples/extensions/.gitignore

@@ -1,2 +1,3 @@
 my_cmd.so
 my_cmd.d
+*.log

docs/source/code_examples/extensions/Makefile

@@ -13,18 +13,18 @@ my_cmd.so: my_cmd.cc
 	$(YOSYS)-config --exec --cxx $(subst $(DATDIR),../../../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
 
 test0.log: my_cmd.so
-	$(YOSYS) -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
+	$(YOSYS) -QTl test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' -f verilog absval_ref.v
 	mv test0.log_new test0.log
 
 test1.log: my_cmd.so
-	$(YOSYS) -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
+	$(YOSYS) -QTl test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' -f verilog absval_ref.v
 	mv test1.log_new test1.log
 
 test1.dot: my_cmd.so
 	$(YOSYS) -m ./my_cmd.so -p 'test1; show -format dot -prefix test1'
 
 test2.log: my_cmd.so
-	$(YOSYS) -Ql test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' sigmap_test.v
+	$(YOSYS) -QTl test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' -f verilog sigmap_test.v
 	mv test2.log_new test2.log
 
 .PHONY: clean

docs/source/yosys_internals/formats/cell_library.rst

@@ -619,6 +619,48 @@ Finite state machines
 
 Add a brief description of the ``$fsm`` cell type.
 
+Coarse arithmetics
+~~~~~~~~~~~~~~~~~~~~~
+
+The ``$macc`` cell type represents a generalized multiply and accumulate operation. The cell is purely combinational. It outputs the result of summing up a sequence of products and other injected summands.
+
+.. code-block::
+
+	Y = 0 +- a0factor1 * a0factor2 +- a1factor1 * a1factor2 +- ...
+	     + B[0] + B[1] + ...
+
+The A port consists of concatenated pairs of multiplier inputs ("factors").
+A zero length factor2 acts as a constant 1, turning factor1 into a simple summand.
+
+In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long.
+
+.. code-block::
+
+	struct A {
+		u(CONFIG.mul_info[0].factor1_len) a0factor1;
+		u(CONFIG.mul_info[0].factor2_len) a0factor2;
+		u(CONFIG.mul_info[1].factor1_len) a1factor1;
+		u(CONFIG.mul_info[1].factor2_len) a1factor2;
+		...
+	};
+
+The cell's ``CONFIG`` parameter determines the layout of cell port ``A``.
+The CONFIG parameter carries the following information:
+
+.. code-block::
+
+	struct CONFIG {
+		u4 num_bits;
+		struct mul_info {
+			bool is_signed;
+			bool is_subtract;
+			u(num_bits) factor1_len;
+			u(num_bits) factor2_len;
+		}[num_ports];
+	};
+
+B is an array of concatenated 1-bit-wide unsigned integers to also be summed up.
+
 Specify rules
 ~~~~~~~~~~~~~
 
@@ -1152,4 +1194,4 @@ file via ABC using the abc pass.
 
 .. todo:: Add information about ``$lut`` and ``$sop`` cells.
 
-.. todo:: Add information about ``$alu``, ``$macc``, ``$fa``, and ``$lcu`` cells.
+.. todo:: Add information about ``$alu``, ``$fa``, and ``$lcu`` cells.

frontends/verific/Makefile.inc

@@ -14,6 +14,7 @@ ifneq ($(DISABLE_VERIFIC_VHDL),1)
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
+	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2019/. share/verific.new/vhdl_vdbs_2019
 endif
 	$(Q) chmod -R a+rX share/verific.new
 	$(Q) mv share/verific.new share/verific