Improve opt_merge performance

kernel/hashlib.h

@@ -21,10 +21,17 @@
 
 namespace hashlib {
 
+#if __cplusplus >= 201603L
+#  define HASHLIB_NODISCARD [[nodiscard]]
+#else
+#  define HASHLIB_NODISCARD
+#endif
+
 const int hashtable_size_trigger = 2;
 const int hashtable_size_factor = 3;
 
 // The XOR version of DJB2
+HASHLIB_NODISCARD
 inline unsigned int mkhash(unsigned int a, unsigned int b) {
 	return ((a << 5) + a) ^ b;
 }
@@ -34,21 +41,27 @@ const unsigned int mkhash_init = 5381;
 
 // The ADD version of DJB2
 // (use this version for cache locality in b)
+HASHLIB_NODISCARD
 inline unsigned int mkhash_add(unsigned int a, unsigned int b) {
 	return ((a << 5) + a) + b;
 }
 
+HASHLIB_NODISCARD
 inline unsigned int mkhash_xorshift(unsigned int a) {
-	if (sizeof(a) == 4) {
-		a ^= a << 13;
-		a ^= a >> 17;
-		a ^= a << 5;
-	} else if (sizeof(a) == 8) {
-		a ^= a << 13;
-		a ^= a >> 7;
-		a ^= a << 17;
-	} else
-		throw std::runtime_error("mkhash_xorshift() only implemented for 32 bit and 64 bit ints");
+	a ^= a << 13;
+	a ^= a >> 17;
+	a ^= a << 5;
+	return a;
+}
+
+HASHLIB_NODISCARD
+inline unsigned long long mkhash_xorshift64(unsigned long long a) {
+	a ^= a << 13;
+	a ^= a >> 17;
+	a ^= a << 5;
+	a ^= a << 13;
+	a ^= a >> 7;
+	a ^= a << 17;
 	return a;
 }
 

kernel/yosys_common.h

@@ -188,6 +188,7 @@ using hashlib::mkhash;
 using hashlib::mkhash_init;
 using hashlib::mkhash_add;
 using hashlib::mkhash_xorshift;
+using hashlib::mkhash_xorshift64;
 using hashlib::hash_ops;
 using hashlib::hash_cstr_ops;
 using hashlib::hash_ptr_ops;

passes/opt/opt_merge.cc

@@ -77,78 +77,47 @@ struct OptMergeWorker
 		return str;
 	}
 
-        uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
+	uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
 	{
-		vector<string> hash_conn_strings;
-		std::string hash_string = cell->type.str() + "\n";
-
-		const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
-		dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
+		uint64_t conn_hash = 0;
 
 		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
 				ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
-			alt_conn = *conn;
-			if (assign_map(alt_conn.at(ID::A)) < assign_map(alt_conn.at(ID::B))) {
-				alt_conn[ID::A] = conn->at(ID::B);
-				alt_conn[ID::B] = conn->at(ID::A);
+			conn_hash = hashlib::mkhash_xorshift64(assign_map(cell->getPort(ID::A)).hash()) \
+							+ hashlib::mkhash_xorshift64(assign_map(cell->getPort(ID::B)).hash());
+		} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+			SigSpec a = assign_map(cell->getPort(ID::A));
+			a.sort();
+			conn_hash = a.hash();
+		} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
+			SigSpec a = assign_map(cell->getPort(ID::A));
+			a.sort_and_unify();
+			conn_hash = a.hash();
+		} else if (cell->type == ID($pmux)) {
+			uint64_t acc = 0;
+			int width = cell->getParam(ID::WIDTH).as_int();
+			SigSpec a = assign_map(cell->getPort(ID::A));
+			SigSpec b = assign_map(cell->getPort(ID::B));
+			SigSpec s = assign_map(cell->getPort(ID::S));
+			for (int i = 0; i < cell->getParam(ID::S_WIDTH).as_int(); i++) {
+				SigSpec b_window = b.extract(i * width, width);
+				acc += mkhash_xorshift64(mkhash(s[i].hash(), b_window.hash()));
 			}
-			conn = &alt_conn;
-		} else
-		if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
-			alt_conn = *conn;
-			assign_map.apply(alt_conn.at(ID::A));
-			alt_conn.at(ID::A).sort();
-			conn = &alt_conn;
-		} else
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
-			alt_conn = *conn;
-			assign_map.apply(alt_conn.at(ID::A));
-			alt_conn.at(ID::A).sort_and_unify();
-			conn = &alt_conn;
-		} else
-		if (cell->type == ID($pmux)) {
-			alt_conn = *conn;
-			assign_map.apply(alt_conn.at(ID::A));
-			assign_map.apply(alt_conn.at(ID::B));
-			assign_map.apply(alt_conn.at(ID::S));
-			sort_pmux_conn(alt_conn);
-			conn = &alt_conn;
+			conn_hash = mkhash_xorshift64(a.hash()) + acc;
+		} else {
+			for (const auto &conn : cell->connections())
+			if (!cell->output(conn.first))
+				conn_hash += mkhash_xorshift64(mkhash(conn.first.hash(), assign_map(conn.second).hash()));
+
+			if (RTLIL::builtin_ff_cell_types().count(cell->type))
+				conn_hash += initvals(cell->getPort(ID::Q)).hash();
 		}
 
-		for (auto &it : *conn) {
-			RTLIL::SigSpec sig;
-			if (cell->output(it.first)) {
-				if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
-					// For the 'Q' output of state elements,
-					//   use its (* init *) attribute value
-					sig = initvals(it.second);
-				}
-				else
-					continue;
-			}
-			else
-				sig = assign_map(it.second);
-			string s = "C " + it.first.str() + "=";
-			for (auto &chunk : sig.chunks()) {
-				if (chunk.wire)
-					s += "{" + chunk.wire->name.str() + " " +
-							int_to_hash_string(chunk.offset) + " " +
-							int_to_hash_string(chunk.width) + "}";
-				else
-					s += RTLIL::Const(chunk.data).as_string();
-			}
-			hash_conn_strings.push_back(s + "\n");
-		}
-
-		for (auto &it : cell->parameters)
-			hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
-
-		std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
+		uint64_t param_hash = 0;
+		for (const auto &it : cell->parameters)
+			param_hash += mkhash_xorshift64(mkhash(it.first.hash(), it.second.hash()));
 
-		for (auto it : hash_conn_strings)
-			hash_string += it;
-
-		return std::hash<std::string>{}(hash_string);
+		return conn_hash + mkhash_xorshift64(param_hash + cell->type.hash());
 	}
 
 	bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
@@ -255,14 +224,19 @@ struct OptMergeWorker
 		while (did_something)
 		{
 			std::vector<RTLIL::Cell*> cells;
-			cells.reserve(module->cells_.size());
-			for (auto &it : module->cells_) {
-				if (!design->selected(module, it.second))
+			cells.reserve(module->cells().size());
+			for (auto cell : module->cells()) {
+				if (!design->selected(module, cell))
+					continue;
+				if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+					// Ignore those for performance: meminit can have an excessively large port,
+					// mem can have an excessively large parameter holding the init data
 					continue;
-				if (mode_keepdc && has_dont_care_initval(it.second))
+				}
+				if (mode_keepdc && has_dont_care_initval(cell))
 					continue;
-				if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
-					cells.push_back(it.second);
+				if (ct.cell_known(cell->type) || (mode_share_all && cell->known()))
+					cells.push_back(cell);
 			}
 
 			did_something = false;