Fix temporal code motion #7959
Fix temporal code motion #7959
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This commit fixes the pass in some cases where llhd.drv value was created
in the same block. The case can be the result of simple verilog code.
For example:
module Mod(input a, input clk, output logic b);
always @(posedge clk) begin
b <= ~a;
end
endmodule
Bug can be reproduced by command:
circt-verilog example.sv | circt-opt --llhd-temporal-code-motion
Signed-off-by: Andrey Vyazovtsev <[email protected]>
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Thanks a lot for finding and fixing this issue!
If you run the llhd-early-code-motion pass before temporal code motion, this will not fail. I was thinking about merging the early code motion and temporal code motion passes into an llhd-simplify-processes pass. Maybe we should do that instead of repeating some of its logic here. It should already properly handle block arguments and CFG loops. WDYT?
| auto *op = arg.getDefiningOp(); | ||
| assert(op && "Using block argument as llhd.drv value is unexpected"); |
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This assumes that passes like block-argument-to-mux are called beforehand. But the pass shouldn't crash if that's not the case, i.e., this should fail with a proper error message or be supported.
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I was thinking about merging
Can I try to implement this? Should old passes be deprecated or removed? Should corresponding files be merged or can we just call passes successively in third file?
That looks it strange but two days ago I tried to use the pass before
I agree with you. It's unclear that |
I think that I was confused due to #7963 issue. The PR may be closed. |
This commit fixes the pass in some cases where llhd.drv value was created
in the same block. The case can be the result of simple verilog code.
For example:
Bug can be reproduced by command:
circt-verilog example.sv | circt-opt --llhd-temporal-code-motion