[ImportVerilog] Support for Procedural assign statements #8010
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| // CHECK: [[TMP1:%.+]] = moore.read %y | ||
| // CHECK: moore.blocking_assign %x, [[TMP1]] : i1 | ||
| assign x = y; |
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Based on SystemVerilog IEEE Std 1800-2017 § 10.6 "Procedural continuous assignments", the assign x = y; should be treated as a continuous assignment.
Therefore, I think maybe we should translate this into moore.assign, rather than moore.blocking_assign. WDYH 🤔? @fabianschuiki
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This pr aims to add support for parsing Procedural assign statements in ImportVerilog.