Openlane Physical Design Workshop Jun22

This workshop focused on a walk-through of Physical Design IC Flow using OpenLANE environment.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault, OpenPhySyn, SPEF-Extractor and custom methodology scripts for design exploration and optimization. OpenLANE includes a suit of open source EDA tools, with the aim to produce clean GDSII without any human intervention. OpenLANE is tuned for Skywater 130nm open-source PDK and can be used to produce hard macros and chips.

In this workshop, we worked to explore and learn the Physical Design Flow for a tutorial RISC-V CPU Design PicoRV32a.

Setting Up the Design:

Synthesis:

Floorplan:

Placement:

Std Cell Layout in Magic:

Running ngspice:

Rise Transition: 20% (0.6V) -> 80% (2.64V)

t(20%) = 2.03e-09 t(80%) = 2.10e-09

Extracting lef