Completely blank project that can be version controlled

README.md

@@ -1 +1,8 @@
-# ParticleFlow
+# ParticleFlow
+
+
+After setting up Vivado (settings and licenses):
+```
+vivado -mode batch -source build.tcl
+vivado ParticeFlow/ParticeFlow.xpr &
+```

build.tcl

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+# Source common utilities
+source -notrace utils.tcl
+
+# Location of hdl
+set hdlRoot hdl
+
+# Set the reference directory for source file relative paths (by default the value is scrip\
+t directory path)                                                                           
+set origin_dir "."
+
+# Set the directory path for the original project from where this script was exported       
+set orig_proj_dir "[file normalize "$origin_dir/"]"
+
+# Create project                                                                            
+create_project -force ParticeFlow ./ParticeFlow
+
+# Set the directory path for the new project                                                
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties                                                                    
+set obj [get_projects ParticeFlow]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "part" "xc7vx690tffg1930-2" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+
+add_files -norecurse $hdlRoot/top.vhd
+
+# If successful, "touch" a file so the make utility will know it's done 
+touch {.setup.done}

hdl/top.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 02/06/2017 11:17:30 AM
+-- Design Name: 
+-- Module Name: top - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+--  Port ( );
+end top;
+
+architecture Behavioral of top is
+
+begin
+
+
+end Behavioral;

utils.tcl

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+# this is a collection of useful project utilities
+
+# implement touch - opens a file updating the time stamp,
+# creating it if it does not exist
+proc touch {f} {
+   set FILEIN [open $f w]
+   close $FILEIN
+}