Avoid undefined conditions in always_comb. #11
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…rified) WIP: Add the set-based flushing functional verification setups WIP: Add set partition table for each thread id; Modify req bypass logic for set partition llc WIP: Add set-partition setups. Verified original functionality. Set-partition is under development. WIP: fix bugs to pass functional testfor set-based functional test; improve parameterization of the code add assertions for parameter Cfg.NumLines and MaxThread for correct functionality WIP: Add python files for automatically generate configuration registers(for set-based partitioning registers) and concat command in axi_llc_config.sv; improve design parameterization WIP: modify partition table calculation logic; add reg address auto-generation for tb WIP: Fix bugs and improve test flow. WIP: Modify python files and makefile to improve automation of register generation and related code generation
…nerated patid tests. Cache Partition: Adjust the width of AXI user signal. Add assumptions to ensure shared region having non-zero size. Add logics to avoid assigning a patid out of range. WIP: Add DUT for synthesis using Resin WIP: modify DUT file WIP: modify DUT file WIP: modify DUT file Change NumLines to 256 and modify makefile Fix the bug for set-flushing and set NumLines to 32 fix bugs and set NumLines to 32 WIP: modify python file for axi_llc_config.sv, set NumLines to 16 set NumLines to 32 Set NumLines to 64 Set NumLines to 256; Add SRAM macro WIP: 256 for synthesis change SRAM macro to behavial model WIP: return to using SRAM Macro fix small typos Fix instantiation typo for SRAM Macro Fix synthesis flow [Design that pass synthesis]
Optimized, synthesizable design v1.0
…on enabled/disabled cache design; Clean up unused files
…bug for odd number of partitions assignment.
Fix LLC partition table calculation bug; Optimize the way of full code automated generation using parameters Cache-Partitioning: Adapt to latest version with randomized user signal. Adapte testbench for partitioning accordingly. Change default testbench to 16 partitions version. make parition_commit register readable,fix tb typo
… in Vivado. Adding initilization values for several registors
… (can be configured via parameter `RemapHash`)
Disable cache partitioning by default.
Fix a problem that causes a latch in synthesis.
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Assign default values in always_comb to avoid undefined conditions.