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restore external clk gen
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@chaoqun-liang
chaoqun-liang committed Feb 20, 2024
1 parent 0d15e42 commit e91ed1f
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Showing 7 changed files with 46 additions and 252 deletions.
3 changes: 0 additions & 3 deletions Bender.yml
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Expand Up @@ -32,8 +32,6 @@ sources:
- gen/eth_idma_reg_top.sv
- rtl/axis_gmii_rx.sv
- rtl/axis_gmii_tx.sv
- rtl/fll_dummy.sv
- rtl/clk_gen_hyper.sv
# Level 1
- rtl/eth_mac_1g_rgmii_fifo.sv
- rtl/eth_mac_1g_rgmii.sv
Expand All @@ -49,7 +47,6 @@ sources:
- rtl/framing_top.sv
- rtl/eth_idma_pkg.sv
- rtl/eth_top.sv
- rtl/eth_clk_gen.sv
- rtl/eth_idma_wrap.sv

- target: any(synthesis, asic)
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61 changes: 0 additions & 61 deletions rtl/clk_gen_hyper.sv
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49 changes: 0 additions & 49 deletions rtl/eth_clk_gen.sv
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2 changes: 1 addition & 1 deletion rtl/eth_idma_pkg.sv
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Expand Up @@ -99,4 +99,4 @@ package eth_idma_pkg;
axis_write_t_chan_padded_t axis;
} write_meta_channel_t;

endpackage : eth_idma_pkg
endpackage : eth_idma_pkg
21 changes: 8 additions & 13 deletions rtl/eth_idma_wrap.sv
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Expand Up @@ -50,6 +50,9 @@ module eth_idma_wrap #(
)(
input logic clk_i,
input logic rst_ni,
/// Etherent Internal clocks
input logic eth_clk_i,
input logic eth_clk90_i,
/// Ethernet: 1000BASE-T RGMII
input logic phy_rx_clk_i,
input logic [3:0] phy_rxd_i,
Expand Down Expand Up @@ -84,7 +87,6 @@ module eth_idma_wrap #(
import eth_idma_reg_pkg::*;
import idma_pkg::*;

logic eth_clk, eth_clk90;
logic idma_req_valid, req_ready, idma_rsp_ready, rsp_valid;

localparam idma_pkg::error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING;
Expand Down Expand Up @@ -204,13 +206,6 @@ module eth_idma_wrap #(
.busy_o ( idma_busy_o )
);

eth_clk_gen i_eth_clk_gen(
.ref_clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_eth_125_o ( eth_clk ),
.clk_eth_125_90_o ( eth_clk90 )
);

eth_top #(
.axi_stream_req_t ( axi_stream_req_t ),
.axi_stream_rsp_t ( axi_stream_rsp_t ),
Expand All @@ -223,8 +218,8 @@ module eth_idma_wrap #(
.hw2reg_itf_t ( eth_idma_hw2reg_t )
) i_eth_top (
.rst_ni ( rst_ni ),
.clk_i ( eth_clk ),
.clk90_int ( eth_clk90 ),
.clk_i ( eth_clk_i ),
.clk90_int ( eth_clk90_i ),
.phy_rx_clk ( phy_rx_clk_i ),
.phy_rxd ( phy_rxd_i ),
.phy_rx_ctl ( phy_rx_ctl_i ),
Expand Down Expand Up @@ -259,7 +254,7 @@ module eth_idma_wrap #(
.src_valid_i ( idma_axis_write_req.tvalid ),
.src_ready_o ( idma_axis_write_rsp.tready ),
.dst_rst_ni ( rst_ni ),
.dst_clk_i ( eth_clk ),
.dst_clk_i ( eth_clk_i ),
.dst_data_o ( eth_axis_tx_req.t ),
.dst_valid_o ( eth_axis_tx_req.tvalid ),
.dst_ready_i ( eth_axis_tx_rsp.tready )
Expand All @@ -271,7 +266,7 @@ module eth_idma_wrap #(
.LOG_DEPTH ( RxFifoLogDepth )
) i_cdc_fifo_rx (
.src_rst_ni ( rst_ni ),
.src_clk_i ( eth_clk ),
.src_clk_i ( eth_clk_i ),
.src_data_i ( eth_axis_rx_rsp.t ),
.src_valid_i ( eth_axis_rx_rsp.tvalid ),
.src_ready_o ( eth_axis_rx_req.tready ),
Expand All @@ -296,4 +291,4 @@ module eth_idma_wrap #(
.mst_resp_i ( axi_rsp_i )
);

endmodule : eth_idma_wrap
endmodule : eth_idma_wrap
73 changes: 37 additions & 36 deletions rtl/eth_top.sv
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Expand Up @@ -11,55 +11,56 @@
`include "register_interface/assign.svh"

module eth_top #(
/// AXI Stream in request struct
parameter type axi_stream_req_t = eth_idma_pkg::axi_stream_req_t,
/// AXI Stream in response struct
parameter type axi_stream_rsp_t = eth_idma_pkg::axi_stream_rsp_t,

/// AXI Stream Data Width
parameter int unsigned DataWidth = 64,
parameter int unsigned DataWidth = 64,
/// AXI Stream Id Width
parameter int unsigned IdWidth = 0,
parameter int unsigned IdWidth = 0,
/// AXI Stream Dest Width = 0
parameter int unsigned DestWidth = 0,
parameter int unsigned DestWidth = 0,
/// AXI Stream User Width
parameter int unsigned UserWidth = 1,
parameter int unsigned UserWidth = 1,
/// Register address width
parameter int unsigned RegAddrWidth = 4,
/// AXI Stream in request struct
parameter type axi_stream_req_t = logic,
/// AXI Stream in response struct
parameter type axi_stream_rsp_t = logic,
/// REGBUS
//parameter type reg2hw_itf_t = eth_idma_reg_pkg::eth_idma_reg2hw_t,
//parameter type hw2reg_itf_t = eth_idma_reg_pkg::eth_idma_hw2reg_t,
parameter type reg2hw_itf_t = logic,
parameter type hw2reg_itf_t = logic,
parameter int AW_REGBUS = 4
parameter type reg2hw_itf_t = logic,
parameter type hw2reg_itf_t = logic

) (
// Internal 125 MHz clock
input wire clk_i,
input wire rst_ni,
input wire clk90_int,
input wire clk_i ,
input wire rst_ni ,
input wire clk90_int ,
// Ethernet: 1000BASE-T RGMII
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
input wire phy_rx_clk ,
input wire [3:0] phy_rxd ,
input wire phy_rx_ctl ,
output wire phy_tx_clk ,
output wire [3:0] phy_txd ,
output wire phy_tx_ctl ,
output wire phy_reset_n ,
input wire phy_int_n ,
input wire phy_pme_n ,
// MDIO
input wire phy_mdio_i,
output reg phy_mdio_o,
output reg phy_mdio_oe,
output wire phy_mdc,
input wire phy_mdio_i ,
output reg phy_mdio_o ,
output reg phy_mdio_oe ,
output wire phy_mdc ,
// AXIS TX/RX
input axi_stream_req_t tx_axis_req_i,
output axi_stream_rsp_t tx_axis_rsp_o,
output axi_stream_req_t rx_axis_req_o,
input axi_stream_rsp_t rx_axis_rsp_i,

input logic idma_req_ready,
input logic idma_rsp_valid,
input logic idma_req_ready,
input logic idma_rsp_valid,
// Reg configs
input reg2hw_itf_t reg2hw_i,
output hw2reg_itf_t hw2reg_o
input reg2hw_itf_t reg2hw_i ,
output hw2reg_itf_t hw2reg_o
);

// ---------------- axis streams for the framing module ----------------------
Expand Down Expand Up @@ -89,7 +90,7 @@ module eth_top #(
.axi_stream_rsp_t ( s_framing_rsp_t ),
.reg2hw_itf_t ( reg2hw_itf_t ),
.hw2reg_itf_t ( hw2reg_itf_t ),
.AW_REGBUS ( AW_REGBUS )
.AW_REGBUS ( RegAddrWidth )
) i_framing_top (
.rst_ni ( rst_ni ),
.clk_i ( clk_i ),
Expand Down Expand Up @@ -164,4 +165,4 @@ module eth_top #(
.out_rsp_i ( rx_axis_rsp_i )
);

endmodule : eth_top
endmodule : eth_top
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