treewide: Miscellaneous changes to bump dependency in Occamy

.github/CODEOWNERS

@@ -5,6 +5,5 @@
 * @paulsc96 @colluca @fischeti
 
 hw/snitch_cluster @paulsc96 @lucabertaccini
-hw/snitch_dma @paulsc96 @thommythomaso
 
 sw @colluca @fischeti @viv-eth

.github/workflows/ci.yml

@@ -39,26 +39,48 @@ jobs:
           cache-to: type=gha,mode=max`
           file: util/container/Dockerfile
           push: true
-          tags: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+          tags: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
 
   ########
   # Docs #
   ########
 
-  docs:
+  build-docs:
     name: Build documentation
     runs-on: ubuntu-22.04
     needs: build-docker
     if: >
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v2
       - name: Build docs
         run: make docs
 
+  deploy-docs:
+    name: Deploy documentation
+    runs-on: ubuntu-22.04
+    needs: build-docker
+    if: github.event_name == 'push' && github.ref == 'refs/heads/main'
+    container:
+      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+    steps:
+      - uses: actions/checkout@v2
+      # For some reason, the checkout is done by a different user,
+      # than that deploying to Github (root, possibly due to Docker).
+      # So we need to set the repository as a safe directory.
+      - name: Git config safe.directory
+        run: |
+          git config --global --add safe.directory $GITHUB_WORKSPACE
+      - name: Generate documentation sources
+        run: |
+          make doc-srcs
+          make doxygen-docs
+      - name: Build and deploy documentation
+        run: mkdocs gh-deploy --force
+
   #####################
   # Python unit tests #
   #####################
@@ -71,7 +93,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v2
       - name: Run pytest
@@ -89,7 +111,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v2
         with:
@@ -140,7 +162,7 @@ jobs:
   #     github.event_name != 'pull_request' ||
   #     github.event.pull_request.head.repo.full_name != github.repository
   #   container:
-  #     image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+  #     image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
   #   steps:
   #     - uses: actions/checkout@v2
   #       with:
@@ -167,7 +189,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v4
         with:

Bender.lock

@@ -7,8 +7,8 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: 4e54ac6766b160217a83a74d5a23af9bbf59e6ee
-    version: null
+    revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
+    version: 0.39.6
     source:
       Git: https://github.com/pulp-platform/axi
     dependencies:
@@ -32,8 +32,8 @@ packages:
     dependencies:
     - common_cells
   cluster_icache:
-    revision: 0e1fb6751d9684d968ba7fb40836e6118b448ecd
-    version: 0.1.1
+    revision: 64e21ae455bbdde850c4df13bef86ea55ac42537
+    version: null
     source:
       Git: https://github.com/pulp-platform/cluster_icache.git
     dependencies:
@@ -50,8 +50,8 @@ packages:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fa2630f61666f61d9d78451c4d8b4d1ea403944e
+    version: 0.2.4
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
@@ -71,7 +71,7 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 1a42da9d5c76f1cff0bcdaaacc474ed85631d734
+    revision: d4010425e943c9845b8549b3c8f8cc8dba73ec47
     version: null
     source:
       Git: https://github.com/pulp-platform/iDMA
@@ -91,8 +91,8 @@ packages:
     - common_cells
     - common_verification
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+    version: 0.4.5
     source:
       Git: https://github.com/pulp-platform/register_interface
     dependencies:

Bender.yml

@@ -19,15 +19,15 @@ package:
     - Matheus Cavalcante <[email protected]>
 
 dependencies:
-  axi:                { git: https://github.com/pulp-platform/axi,                rev:  4e54ac6766b160217a83a74d5a23af9bbf59e6ee  }
+  axi:                { git: https://github.com/pulp-platform/axi,                version:  0.39.6  }
   axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0   }
   common_cells:       { git: https://github.com/pulp-platform/common_cells,       version:  1.35.0  }
   FPnew:              { git: "https://github.com/pulp-platform/cvfpu.git",        rev:      pulp-v0.1.3 }
   register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2   }
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.11  }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0   }
-  cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, version:  0.1.0   }
-  idma:               { git: https://github.com/pulp-platform/iDMA,               rev: __deploy__9cbcd30__snitch-tracing }
+  cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 }
+  idma:               { git: https://github.com/pulp-platform/iDMA,               rev: __deploy__110fd06__master }
 
 export_include_dirs:
   - hw/reqrsp_interface/include
@@ -184,9 +184,9 @@ sources:
       - target/common/test/tb_bin.sv
 
   # target/snitch_cluster
-  - target: snitch_cluster
+  - target: snitch_cluster_wrapper
     files:
       - target/snitch_cluster/generated/snitch_cluster_wrapper.sv
-  - target: all(snitch_cluster, any(simulation, verilator))
+  - target: all(snitch_cluster_wrapper, any(simulation, verilator))
     files:
       - target/snitch_cluster/test/testharness.sv

Makefile

@@ -27,7 +27,7 @@ ROOT = $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
 ############
 
 NONFREE_REMOTE ?= [email protected]:pulp-restricted/snitch-cluster-nonfree.git
-NONFREE_COMMIT ?= e30961e20a23a76442da27d2ba07c9fe20f3b575
+NONFREE_COMMIT ?= 35cdb5b03778d3ec52e6d8fa0856ee789489b25a
 NONFREE_DIR = $(ROOT)/nonfree
 
 all: nonfree

docs/ug/trace_analysis.md

@@ -128,6 +128,7 @@ In the following table you can find a complete list of all the performance metri
 |`snitch_issues`           |Total number of instructions issued by Snitch, excluding those offloaded to the FPSS (see `snitch_fseq_offloads`).                                                                                  |
 |`snitch_fseq_offloads`    |Total number of instructions offloaded by Snitch to the FPSS.                                                                                                                                       |
 |`snitch_fseq_rel_offloads`|The ratio between `snitch_fseq_offloads` and the total number of instructions issued by Snitch core proper, i.e. `snitch_issues + snitch_fseq_offloads`.                                            |
+|`snitch_occupancy`        |IPC of the Snitch core, calculated as `snitch_issues / cycles`.                                                                                                                                     |
 |`fpss_issues`             |Total number of instructions issued by the FPSS. It counts repeated issues from the FREP sequencer.                                                                                                 |
 |`fpss_fpu_issues`         |Similar to `fpss_issues`, but counts only instructions destined to the FPU proper. It does not for instance include instructions issued to the FPSS's LSU.                                          |
 |`fseq_yield`              |The ratio between `fpss_issues` and `snitch_fseq_offloads`. The difference lies in the FREP sequencer possibly replicating instructions. If the sequencer is not used this ratio should amount to 1.|

hw/snitch_cluster/src/snitch_cluster.sv

@@ -22,6 +22,7 @@
 /// Snitch Cluster Top-Level.
 module snitch_cluster
   import snitch_pkg::*;
+  import snitch_icache_pkg::*;
 #(
   /// Width of physical address.
   parameter int unsigned PhysicalAddrWidth  = 48,
@@ -63,8 +64,8 @@ module snitch_cluster
   parameter int unsigned ICacheLineWidth [NrHives] = '{default: 0},
   /// Number of icache lines per set.
   parameter int unsigned ICacheLineCount [NrHives] = '{default: 0},
-  /// Number of icache sets.
-  parameter int unsigned ICacheSets [NrHives]      = '{default: 0},
+  /// Number of icache ways.
+  parameter int unsigned ICacheWays [NrHives]      = '{default: 0},
   /// Enable virtual memory support.
   parameter bit          VMSupport          = 1,
   /// Per-core enabling of the standard `E` ISA reduced-register extension.
@@ -510,10 +511,10 @@ module snitch_cluster
   tcdm_req_t [NrTCDMPortsCores-1:0] tcdm_req;
   tcdm_rsp_t [NrTCDMPortsCores-1:0] tcdm_rsp;
 
-  core_events_t [NrCores-1:0]                      core_events;
-  tcdm_events_t                                    tcdm_events;
-  dma_events_t [DMANumChannels-1:0]                dma_events;
-  snitch_icache_pkg::icache_events_t [NrCores-1:0] icache_events;
+  core_events_t      [NrCores-1:0]        core_events;
+  tcdm_events_t                           tcdm_events;
+  dma_events_t       [DMANumChannels-1:0] dma_events;
+  icache_l0_events_t [NrCores-1:0]        icache_events;
 
   // 4. Memory Subsystem (Core side).
   reqrsp_req_t [NrCores-1:0] core_req;
@@ -969,7 +970,7 @@ module snitch_cluster
       hive_req_t [HiveSize-1:0] hive_req_reshape;
       hive_rsp_t [HiveSize-1:0] hive_rsp_reshape;
 
-      snitch_icache_pkg::icache_events_t [HiveSize-1:0] icache_events_reshape;
+      icache_l0_events_t [HiveSize-1:0] icache_events_reshape;
 
       for (genvar j = 0; j < NrCores; j++) begin : gen_hive_matrix
         // Check whether the core actually belongs to the current hive.
@@ -993,7 +994,7 @@ module snitch_cluster
         .CoreCount (HiveSize),
         .ICacheLineWidth (ICacheLineWidth[i]),
         .ICacheLineCount (ICacheLineCount[i]),
-        .ICacheSets (ICacheSets[i]),
+        .ICacheWays (ICacheWays[i]),
         .IsoCrossing (IsoCrossing),
         .sram_cfg_t  (sram_cfg_t),
         .sram_cfgs_t (sram_cfgs_t),

hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv

@@ -8,6 +8,7 @@
 
 module snitch_cluster_peripheral
   import snitch_pkg::*;
+  import snitch_icache_pkg::*;
   import snitch_cluster_peripheral_reg_pkg::*;
 #(
   // Nr of cores in the cluster
@@ -31,13 +32,13 @@ module snitch_cluster_peripheral
   input  core_events_t [NrCores-1:0]                      core_events_i,
   input  tcdm_events_t                                    tcdm_events_i,
   input  dma_events_t [DMANumChannels-1:0]                dma_events_i,
-  input  snitch_icache_pkg::icache_events_t [NrCores-1:0] icache_events_i
+  input  icache_l0_events_t [NrCores-1:0] icache_events_i
 );
 
   // Pipeline register to ease timing.
   tcdm_events_t tcdm_events_q;
   dma_events_t [DMANumChannels-1:0] dma_events_q;
-  snitch_icache_pkg::icache_events_t [NrCores-1:0] icache_events_q;
+  icache_l0_events_t [NrCores-1:0] icache_events_q;
   `FF(tcdm_events_q, tcdm_events_i, '0)
   `FF(dma_events_q, dma_events_i, '0)
   `FF(icache_events_q, icache_events_i, '0)

hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl

@@ -66,7 +66,7 @@ package ${cfg['pkg_name']};
 
   localparam int unsigned ICacheLineWidth [NrHives] = '{${icache_cfg('cacheline')}};
   localparam int unsigned ICacheLineCount [NrHives] = '{${icache_cfg('depth')}};
-  localparam int unsigned ICacheSets [NrHives] = '{${icache_cfg('sets')}};
+  localparam int unsigned ICacheWays [NrHives] = '{${icache_cfg('ways')}};
 
   localparam int unsigned Hive [NrCores] = '{${core_cfg('hive')}};
 
@@ -277,7 +277,7 @@ module ${cfg['name']}_wrapper (
     .DMANumChannels (${cfg['dma_nr_channels']}),
     .ICacheLineWidth (${cfg['pkg_name']}::ICacheLineWidth),
     .ICacheLineCount (${cfg['pkg_name']}::ICacheLineCount),
-    .ICacheSets (${cfg['pkg_name']}::ICacheSets),
+    .ICacheWays (${cfg['pkg_name']}::ICacheWays),
     .VMSupport (${int(cfg['vm_support'])}),
     .RVE (${core_isa('e')}),
     .RVF (${core_isa('f')}),

hw/snitch_cluster/src/snitch_hive.sv

@@ -7,15 +7,15 @@
 `include "snitch_vm/typedef.svh"
 
 /// Shared subsystems for `CoreCount` cores.
-module snitch_hive #(
+module snitch_hive import snitch_icache_pkg::*; #(
   /// Number of cores which share an instruction frontend
   parameter int unsigned CoreCount          = 4,
   /// Width of a single icache line.
   parameter int unsigned ICacheLineWidth    = CoreCount > 2 ? CoreCount * 32 : 64,
   /// Number of icache lines per set.
   parameter int unsigned ICacheLineCount    = 128,
-  /// Number of icache sets.
-  parameter int unsigned ICacheSets         = 4,
+  /// Number of icache ways.
+  parameter int unsigned ICacheWays         = 4,
   parameter bit          IsoCrossing        = 1,
   /// Address width of the buses
   parameter int unsigned AddrWidth          = 0,
@@ -53,7 +53,7 @@ module snitch_hive #(
 
   input sram_cfgs_t sram_cfgs_i,
 
-  output snitch_icache_pkg::icache_events_t [CoreCount-1:0] icache_events_o
+  output icache_l0_events_t [CoreCount-1:0] icache_events_o
 );
   // Extend the ID to route back results to the appropriate core.
   localparam int unsigned IdWidth = 5;
@@ -87,7 +87,7 @@ module snitch_hive #(
     .L0_LINE_COUNT      ( 8                ),
     .LINE_WIDTH         ( ICacheLineWidth  ),
     .LINE_COUNT         ( ICacheLineCount  ),
-    .SET_COUNT          ( ICacheSets       ),
+    .WAY_COUNT          ( ICacheWays       ),
     .FETCH_AW           ( AddrWidth        ),
     .FETCH_DW           ( 32               ),
     .FILL_AW            ( AddrWidth        ),
@@ -107,7 +107,8 @@ module snitch_hive #(
     .clk_d2_i (clk_d2_i),
     .rst_ni (rst_ni),
     .enable_prefetching_i ( icache_prefetch_enable_i ),
-    .icache_events_o  ( icache_events_o),
+    .icache_l0_events_o   ( icache_events_o),
+    .icache_l1_events_o   ( ),
     .flush_valid_i    ( flush_valid    ),
     .flush_ready_o    ( flush_ready    ),
 

sw/snRuntime/api/cls_decls.h

@@ -10,6 +10,7 @@
 
 typedef struct {
     uint32_t hw_barrier;
+    uint32_t reduction;
     snrt_allocator_t l1_allocator;
 } cls_t;
 

sw/snRuntime/api/riscv_decls.h

@@ -6,9 +6,9 @@
 
 #include <stdint.h>
 
-static inline void snrt_wfi();
+inline void snrt_wfi();
 
-static inline uint32_t snrt_mcycle();
+inline uint32_t snrt_mcycle();
 
 inline void snrt_interrupt_enable(uint32_t irq);
 

sw/snRuntime/api/sync_decls.h

@@ -28,3 +28,5 @@ inline void snrt_cluster_hw_barrier();
 inline void snrt_global_barrier();
 
 inline uint32_t snrt_global_all_to_all_reduction(uint32_t value);
+
+inline void snrt_wait_writeback(uint32_t val);

sw/snRuntime/src/start.c

@@ -23,6 +23,7 @@ static inline void snrt_init_tls() {
         // First initialize the DM core's .tdata section from main memory
         asm volatile("mv %0, tp" : "=r"(tls_ptr) : :);
         snrt_dma_start_1d((void*)tls_ptr, (void*)(&__tdata_start), size);
+        snrt_dma_wait_all();
 
         // Then initialize all other cores' .tdata sections from the DM
         // core's. The offset between the TLS section of successive cores