STFT Pulse Generator
Novel and future approaches for Mølmer-Sørensen-style or geometric phase gates can require complex pulse spectra on several frequency bands. The STFT pulse generator is designed to synthesize such spectra and emit the pulses with deterministic timing. The tone amplitude, frequency and phase relations can all be specified with high precision.
The architecture makes use of a number of combined signal sources with several Intermediate Frequencies (IFs). By modulating complex signals onto a final analog RF carrier, the spectrum can be shaped in the baseband with minimal undesired spectral components in the RF. As a compromise between complexity and functionality, 3 sets of 1024 tones with customizable tone-spacing can be placed in a 400MHz window. This window can itself be placed somewhere within [−400, 400]MHz from the [0.3, 4.8]GHz carrier. This combination allows for a spectral composition in which carrier leakage and I/Q imbalance artifacts will show up far away from the desired spectral components. The following shows an exemplary output of the device on a spectrum analyzer:
The high level block diagram depicts the main signal processing blocks with the parameters listed in the table below. The main signal computation consists of 3 STFT branches. Each branch contains one block-FFT (note that FFT in this context usually refers to an inverse FFT) core with repeater, two interpolators for real and complex signal components and one DUC, illustrated as sinusoidal signal source and multiplier. Each FFT core gets a set of 1024 complex frequency parameters [a_-512,a_511] which are transformed into a time-domain representation. The FFT output is then continuously repeated and fed into the variable interpolators. As short temporal blocks are stitched together, we call this a Short-Time Fourier Transform (STFT). The interpolators compute the missing samples to the full 500MSps at which the DAC is driven. Valid interpolation rates N are 2 and multiples of 4. The output of each interpolator is finally upconverted by the frequency f_0 which can be specified at mHz resolution in a [-250,250]MHz interval.
The outputs of the STFT branches are summed up and then multiplied with the output of the window signal path. As the window path is only real-valued, real and complex signal parts of the branches are both multiplied by the same signal. The window features the same block-FFT core as the branches with the imaginary time-domain output being discarded. The real part is interpolated by another interpolator with a maximum rate-change of K=8192. This window can be gated and triggered with deterministic latency. After being transferred to the DAC, the signal is interpolated again to 1GSps and upconverted by f_1 = [-500, 500]MHz. The DAC then converts the real and complex signals to the analog domain and drives the I and Q inputs of a final, analog I/Q modulator. The RF input of the modulator is fed by a Phase-Locked Loop (PLL) that can synthesize a frequency in the f_2 = [0.3,4.8]GHz range.
| Parameter | Description | Constraint |
|---|---|---|
| R | base sample rate | fixed 500MHz |
| M | FFT size | fixed 1024 |
| P | number repeated windows | integer |
| N | branch upsampling factor | 2, 4, 8, 12, …, 1024 |
| K | window upsampling factor | 2, 4, 8, 12, …, 8192 |
| am | branch FFT tone parameters | complex 2x16bit fixed-point |
| bm | window FFT parameters | complex 2x16bit fixed-point |
| f0 | internal DDS frequency | [ − 250, 250]MHz |
| f1 | DAC DDS frequency | [ − 500, 500]MHz |
| f2 | PLL LO frequency | [0.3, 4.8]GHz |
| tpulse | pulse time | tpuls*e = M ⋅ P ⋅ N ⋅ (1/R) |
| fΔ | frequency spacing | fΔ = R/(M ⋅ N) |
| Bbranch | branch bandwidth | Bbranch = R/N |
| fm | tone frequency after upconversion | fm = f0 + f1 + f2 ± m ⋅ fΔ |
| Module | Parameter | Specification |
|---|---|---|
| General | output sample rate | 500MSps |
| data width | 16 bit | |
| FFT | size | 1024 |
| arbitrary single tone SNR/SFDR | >90dB/100dB | |
| arbitrary 8 tone SNR/SFDR | >70dB/90dB | |
| arbitrary 128 tone SNR/SFDR | >60dB/70dB | |
| Interpolator | image rejection | >89.5dB |
| passband droop | <0.9dB/10% | |
| input cutoff frequency | 0.8fN (80% Nyquist) | |
| supported branch interpolation rates | 2, 4, 8, 12, …, 1024 | |
| suppoted window interpolation rates | 2, 4, 8, 12, …, 8192 | |
| Upconverter | frequency resolution | 58mHz |
| frequency range | [-250, 250]MHz | |
| SNR/SFDR | >83dB/84dB |
The STFT pulse generator driver Application Programming Interface (API) exposes the gateware configuration in convenient kernel functions. This section will give a functional overview over the API functions and their usage. For the exact parameter definitions see API documentation.
Each FFT in the pulse generator can be loaded, cleared, started and
configured individually. The send_full_coef() function can be used to
send a full 1024 point coefficient vector to a specific FFT core.
stage_coef_adr() and stage_coef_data() will stage FFT address and
data on Kasli until a send_frame() call transfers them to their
destination FFT memory. This allows for up to 13 consecutive
coefficients to be written to an offset in a specified FFT core.
start_fft() will trigger the FFT computation in a core.
set_shiftmask() allows the specification of a scaling schedule for
each FFT.
Signal processing parameters can be specified for each STFT branch
individually. The API provides set_duc_frequency() to set the DUC
frequency, set_duc_phase() to set the DUC phase and
set_interpolation_rate() to set the branch interpolation rate. The
window FFT and interpolation rate can be configured in a similar manner,
being identified as a fourth FFT and interpolator.
set_number_repeats() allows the window to be repeated a number of
times.
set_pulsesettings() allows the pulse generator to either:
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continuously output the accumulated branch signals.
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continuously output the windowed branch signals, infinitely repeating the window.
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output the windowed signal a specified number of times when the pulse is triggered.
If the pulse generator is configured to the third option, the
trigger() function will trigger the emission of a pulse as soon as
possible – either as soon as all pending FFT computations are done or as
soon as the trigger register in the Phaser FPGA is written. However,
because Kasli and Phaser are connected using a frame-based real-time
interface, the exact frame timing is crucial for a deterministic
latency. Using the get_frame_timestamp() function, the exact timing of
a frame can be stored in self.frame_tstamp and the trigger()
function can schedule the trigger flag to be sent an exact integer
multiple of self.tframe later, resulting in deterministic latency.
There are a couple of important considerations when configuring the STFT pulse generator. The combination of various DSP components and their inherent dynamics impose constraints on the valid parameters. Since some of the constraints are very dynamic, it is not practical to inhibit all erroneous constellations. The user therefore has to be cognizant of the limitations and interactions in the architecture.
Digital circuits are limited in their ability to represent signals. If signal amplitude/frequency fall outside the allowed intervals, overflow/aliasing will occur. In an aliasing condition, spectral content outside the representable bandwidth will appear somewhere within the representable region. If a signal overflows (i.e. a sample is outside the allowed value range), the output will be discontinuous, resulting in strong harmonic distortion. While these effects can be tolerated or even useful if accounted for, interpreting the output of an overflowing/aliasing circuit can be questioning if not taken into account.
Overflow can happen at three places in the STFT pulse generator. The first and most nuanced is within the FFT computation. Since the usual computation of an inverse Discrete Fourier Transform (DFT) involves a 1/N factor and the FFT works in several stages, the 1/N factor is usually achieved by bitshifting the intermediate signals by one in every stage. The 1/2 factors in every stage compound to 1/N at the end of the FFT. With only a limited number of tones or small tone coefficients, it is usually desirable to scale the output for maximum signal power and hence SNR. This can be achieved by omitting the 1/2 factor in some FFT stages. However, depending on the combination of coefficients and shiftmask, the signal might overflow at the output or during the computation. While better shifting schedules can be designed for special cases, the following usually yields adequate performance without the risk of overflow:
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The total scaling should be lower (next power of two) than the sum of the coefficient magnitudes.
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Scaling must generally happen in the later stages to avoid overflow in the intermediate stages.
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However, the first two stages can always be scaled (unless more than 256 tones are present).
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The magnitude of each individual coefficient should not be greater than 1 (i.e. 1 + 1j should be avoided).
The second place overflow can occur is at the adders summing up the branch outputs where it will happen if the sum of the branch outputs does not fit into the 16 bit representation. Lastly, the FIR filters in the interpolators display inevitable overshoot for abrupt signal changes. If the time-domain output of an FFT is such that there is a step change close to the highest or lowest representable amplitude, the signal will overflow. With interpolation rates greater than 4, the effect will be suppressed by an additional Cascaded Integrator Comb (CIC) filter. It will still produce unintended spectral components.
Aliasing has to be considered at the two digital upconverters in the architecture. The "baseband" signal after the branch interpolator will occupy a bandwidth proportional to the interpolation rate and defined by the FFT coefficients. If spectral content is upconverted to outside the [-250, 250]MHz window representable in a complex 500MSps signal, it will alias. Similarly, if spectral content falls outside the [-500, 500]MHz window representable after the DAC upconverter (f_1), the signal will alias at this point.
Finally, the digital filters in the branch interpolator can only be built with a transition band, attenuating the highest frequencies. For both branch- and DAC interpolator, the transition band starts at 80% of the input Nyquist frequency, meaning frequencies higher than this should not be present at the input. For the branches and window this simply means, that the highest and lowest 10% of the coefficients should be set to zero. Unfortunately the transition band of the DAC interpolator is more difficult to avoid and the user has to make sure that none of the upconverted tones of either branch lie outside the [-200, 200]MHz DAC interpolator passband.