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iHP0p2: updated files for iHP process
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@@ -14,28 +14,85 @@ jobs: | |
| submodules: recursive | ||
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| - name: Build GDS | ||
| uses: TinyTapeout/tt-gds-action@tt09 | ||
| with: | ||
| flow: openlane2 | ||
| uses: TinyTapeout/tt-gds-action/orfs@tt09 | ||
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| precheck: | ||
| needs: gds | ||
| runs-on: ubuntu-24.04 | ||
| steps: | ||
| - name: Run Tiny Tapeout Precheck | ||
| uses: TinyTapeout/tt-gds-action/precheck@tt09 | ||
| #precheck: | ||
| # needs: gds | ||
| # runs-on: ubuntu-24.04 | ||
| # steps: | ||
| # - name: Run Tiny Tapeout Precheck | ||
| # uses: TinyTapeout/tt-gds-action/precheck@tt09 | ||
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| gl_test: | ||
| needs: gds | ||
| runs-on: ubuntu-24.04 | ||
| steps: | ||
| - name: checkout repo | ||
| uses: actions/checkout@v4 | ||
| with: | ||
| submodules: recursive | ||
| needs: gds | ||
| runs-on: ubuntu-24.04 | ||
| env: | ||
| PDK_ROOT: ${{ github.workspace }}/IHP-Open-PDK | ||
| TEST_DIR: ${{ github.workspace }}/test | ||
| steps: | ||
| - name: checkout repo | ||
| uses: actions/checkout@v4 | ||
| with: | ||
| submodules: recursive | ||
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| - name: Download GDS artifact | ||
| uses: actions/download-artifact@v4 | ||
| with: | ||
| name: tt_submission | ||
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| - name: install PDK | ||
| uses: actions/checkout@v4 | ||
| with: | ||
| repository: tinytapeout/IHP-Open-PDK | ||
| ref: tt | ||
| path: IHP-Open-PDK | ||
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| - name: Setup python | ||
| uses: actions/setup-python@v5 | ||
| with: | ||
| python-version: '3.11' | ||
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| - name: Install Python packages | ||
| shell: bash | ||
| run: pip install -r test/requirements.txt | ||
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| - name: ccache | ||
| uses: hendrikmuhs/[email protected] | ||
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| - name: Install iverilog | ||
| shell: bash | ||
| run: | | ||
| wget https://github.com/htfab/iverilog/releases/download/13.0-git-d8c3c51/iverilog_13.0-git-d8c3c51a-1_amd64.deb | ||
| sudo apt-get update -y | ||
| sudo apt-get install -y ./iverilog_13.0-git-d8c3c51a-1_amd64.deb | ||
| - name: Run tests | ||
| shell: bash | ||
| run: | | ||
| cp tt_submission/*.v "$TEST_DIR/gate_level_netlist.v" | ||
| cd "$TEST_DIR" | ||
| rm -f tb.vcd results.xml | ||
| make clean | ||
| GATES=yes make | ||
| # `make` will return success even if the tests fail, so check for failure in results.xml | ||
| test -f results.xml | ||
| ! grep failure results.xml | ||
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| - name: Upload VCD | ||
| if: always() | ||
| uses: actions/upload-artifact@v4 | ||
| with: | ||
| name: gatelevel_test_vcd | ||
| path: | | ||
| ${{ env.TEST_DIR }}/tb.vcd | ||
| ${{ env.TEST_DIR }}/results.xml | ||
| - name: GL test | ||
| uses: TinyTapeout/tt-gds-action/gl_test@tt09 | ||
| - name: Test Summary | ||
| if: always() | ||
| uses: test-summary/[email protected] | ||
| with: | ||
| paths: ${{ env.TEST_DIR }}/results.xml | ||
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| viewer: | ||
| needs: gds | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -1,51 +1,37 @@ | ||
| `default_nettype none | ||
| `timescale 1ns/1ps | ||
| `timescale 1ns / 1ps | ||
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| /* | ||
| this testbench just instantiates the module and makes some convenient wires | ||
| that can be driven / tested by the cocotb test.py | ||
| /* This testbench just instantiates the module and makes some convenient wires | ||
| that can be driven / tested by the cocotb test.py. | ||
| */ | ||
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| // testbench is controlled by test.py | ||
| module tb (); | ||
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| // this part dumps the trace to a vcd file that can be viewed with GTKWave | ||
| initial begin | ||
| $dumpfile ("tb.vcd"); | ||
| $dumpvars (0, tb); | ||
| #1; | ||
| end | ||
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| // wire up the inputs and outputs | ||
| wire [7:0] ui_in; | ||
| wire [7:0] uo_out; | ||
| wire [7:0] uio_in; | ||
| wire [7:0] uio_out; | ||
| wire [7:0] uio_oe; | ||
| wire clk; | ||
| wire rst_n; | ||
| wire ena; | ||
| `ifdef GL_TEST | ||
| wire VPWR = 1'b1; | ||
| wire VGND = 1'b0; | ||
| `endif | ||
| // Dump the signals to a VCD file. You can view it with gtkwave. | ||
| initial begin | ||
| $dumpfile("tb.vcd"); | ||
| $dumpvars(0, tb); | ||
| #1; | ||
| end | ||
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| // Wire up the inputs and outputs: | ||
| reg clk; | ||
| reg rst_n; | ||
| reg ena; | ||
| reg [7:0] ui_in; | ||
| reg [7:0] uio_in; | ||
| wire [7:0] uo_out; | ||
| wire [7:0] uio_out; | ||
| wire [7:0] uio_oe; | ||
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| tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut | ||
| ( | ||
| // include power ports for the Gate Level test | ||
| `ifdef GL_TEST | ||
| .VPWR(VPWR), | ||
| .VGND(VGND), | ||
| `endif | ||
| .ui_in (ui_in), // Dedicated inputs | ||
| .uo_out (uo_out), // Dedicated outputs | ||
| .uio_in (uio_in), // IOs: Input path | ||
| .uio_out (uio_out), // IOs: Output path | ||
| .uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output) | ||
| .ena (ena), // enable - goes high when design is selected | ||
| .clk (clk), // clock | ||
| .rst_n (rst_n) // not reset | ||
| ); | ||
| tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut ( | ||
| .ui_in (ui_in), // Dedicated inputs | ||
| .uo_out (uo_out), // Dedicated outputs | ||
| .uio_in (uio_in), // IOs: Input path | ||
| .uio_out(uio_out), // IOs: Output path | ||
| .uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output) | ||
| .ena (ena), // enable - goes high when design is selected | ||
| .clk (clk), // clock | ||
| .rst_n (rst_n) // not reset | ||
| ); | ||
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| endmodule |