Fix cppcheck warnings

hal/hifive1.c

@@ -55,28 +55,28 @@
 
 /* QSPI Fields */
 #define FESPI_IP_TXWM             0x1
-#define FESPI_RXDATA_FIFO_EMPTY   (1 << 31)
-#define FESPI_TXDATA_FIFO_FULL    (1 << 31)
-#define FESPI_FMT_DIR_TX          (1 << 3)
+#define FESPI_RXDATA_FIFO_EMPTY   (1UL << 31)
+#define FESPI_TXDATA_FIFO_FULL    (1UL << 31)
+#define FESPI_FMT_DIR_TX          (1UL << 3)
 
 #define FESPI_CSMODE_AUTO         0x0UL
 #define FESPI_CSMODE_HOLD         0x2UL
 #define FESPI_CSMODE_MASK         0x3UL
 
 #define FESPI_FCTRL_MODE_SEL      0x1UL
 
-#define FESPI_FFMT_CMD_EN         0x1
-#define FESPI_FFMT_ADDR_LEN(x)    (((x) & 0x7) << 1)
-#define FESPI_FFMT_PAD_CNT(x)     (((x) & 0xf) << 4)
-#define FESPI_FFMT_CMD_PROTO(x)   (((x) & 0x3) << 8)
-#define FESPI_FFMT_ADDR_PROTO(x)  (((x) & 0x3) << 10)
-#define FESPI_FFMT_DATA_PROTO(x)  (((x) & 0x3) << 12)
-#define FESPI_FFMT_CMD_CODE(x)    (((x) & 0xff) << 16)
-#define FESPI_FFMT_PAD_CODE(x)    (((x) & 0xff) << 24)
+#define FESPI_FFMT_CMD_EN         0x1UL
+#define FESPI_FFMT_ADDR_LEN(x)    (((x) & 0x7) << 1UL)
+#define FESPI_FFMT_PAD_CNT(x)     (((x) & 0xf) << 4UL)
+#define FESPI_FFMT_CMD_PROTO(x)   (((x) & 0x3) << 8UL)
+#define FESPI_FFMT_ADDR_PROTO(x)  (((x) & 0x3) << 10UL)
+#define FESPI_FFMT_DATA_PROTO(x)  (((x) & 0x3) << 12UL)
+#define FESPI_FFMT_CMD_CODE(x)    (((x) & 0xff) << 16UL)
+#define FESPI_FFMT_PAD_CODE(x)    (((x) & 0xff) << 24UL)
 
-#define FESPI_SCKDIV_MASK         0xFFF
+#define FESPI_SCKDIV_MASK         0xFFFUL
 
-#define FESPI_TXMARK_MASK         0x3
+#define FESPI_TXMARK_MASK         0x3UL
 
 /* FESPI_REG_FMT Fields */
 /* SPI I/O direction */
@@ -104,11 +104,11 @@
 #endif
 
 /* SPI flash status fields (from FESPI_READ_STATUS command) */
-#define FESPI_RX_BSY              (1 << 0)
-#define FESPI_RX_WE               (1 << 1)
+#define FESPI_RX_BSY              (1 << 0UL)
+#define FESPI_RX_WE               (1 << 1UL)
 
 /* QSPI Flash Sector Size */
-#define FESPI_FLASH_SECTOR_SIZE   (4 * 1024)
+#define FESPI_FLASH_SECTOR_SIZE   (4 * 1024UL)
 
 
 /* PRCI Registers */
@@ -135,8 +135,8 @@
 
 #define HFROSCCFG_DIV            0x0000001FUL
 #define HFROSCCFG_TRIM           0x001F0000UL
-#define HFROSCCFG_EN             (1UL << 30)
-#define HFROSCCFG_READY          (1UL << 31)
+#define HFROSCCFG_EN             (1UL << 30UL)
+#define HFROSCCFG_READY          (1UL << 31UL)
 #define HFROSCCFG_DIV_SHIFT(d)   ((d << 0) & HFROSCCFG_TRIM)
 #define HFROSCCFG_TRIM_SHIFT(t)  ((t << 16) & HFROSCCFG_TRIM)
 
@@ -154,19 +154,19 @@
 #define UART_REG_DIV            (*(volatile uint32_t *)(UART0_BASE + 0x18))
 
 /* TXDATA Fields */
-#define UART_TXEN               (1 <<  0)
-#define UART_TXFULL             (1 << 31)
+#define UART_TXEN               (1UL <<  0)
+#define UART_TXFULL             (1UL << 31)
 
 /* RXDATA Fields */
-#define UART_RXEN               (1 <<  0)
-#define UART_RXEMPTY            (1 << 31)
+#define UART_RXEN               (1UL <<  0)
+#define UART_RXEMPTY            (1UL << 31)
 
 /* TXCTRL Fields */
-#define UART_NSTOP              (1 <<  1)
-#define UART_TXCNT(count)       ((0x7 & count) << 16)
+#define UART_NSTOP              (1UL <<  1)
+#define UART_TXCNT(count)       ((0x7UL & count) << 16)
 
 /* IP Fields */
-#define UART_TXWM               (1 <<  0)
+#define UART_TXWM               (1UL <<  0)
 
 
 /* Configuration Defaults */
@@ -183,16 +183,16 @@
 /* PLL Configuration */
 /* R and Q are fixed values for this PLL code */
 #define PLL_R (1)  /* First Divisor: By 2 (takes 16Mhz PLLREF / 2 = 8MHz) */
-#define PLL_F(cpuHz) (((cpuHz / PLLREF_FREQ) * 2) - 1) /* Multiplier */
+#define PLL_F(cpuHz) (((cpuHz / PLLREF_FREQ) * 2U) - 1U) /* Multiplier */
 #define PLL_Q (1)  /* Second Divisor: By 2 */
 
 /* SPI Serial clock divisor */
-#define FESPI_SCKDIV_DEFAULT   0x03
-#define FESPI_SCKDIV_VAL(cpuHz, flashHz) (cpuHz / ((2 * flashHz) - 1))
+#define FESPI_SCKDIV_DEFAULT   0x03U
+#define FESPI_SCKDIV_VAL(cpuHz, flashHz) (cpuHz / ((2U * flashHz) - 1U))
 
 /* UART baud initialize value */
 #ifndef UART_BAUD_INIT
-#define UART_BAUD_INIT 115200
+#define UART_BAUD_INIT 115200U
 #endif
 
 

hal/nxp_p1021.c

@@ -194,7 +194,7 @@ static int test_tpm(void);
 #define UART_LSR_THRE (0x20) /* Transmitter holding register empty */
 
 /* P1021 eLBC (Enhanced Local Bus Controller) - RM 12.3 */
-#define ELBC_BASE        (CCSRBAR + 0x5000)
+#define ELBC_BASE        (CCSRBAR + 0x5000UL)
 #define ELBC_MAX_BANKS   8
 #define ELBC_BANK_SZ     8192
 
@@ -216,51 +216,51 @@ static int test_tpm(void);
 #define ELBC_LTEATR ((volatile uint32_t*)(ELBC_BASE + 0xBC))  /* transfer error attributes register */
 
 
-#define ELBC_BR_ADDR(n)   (((uint32_t)n) & 0xFFFF8000) /* Physical base address - upper 17-bits */
-#define ELBC_BR_PS(n)     (((n) & 0x3) << 11) /* port size - 1=8-bit, 2=16-bit */
-#define ELBC_BR_DECC(n)   (((n) & 0x3) << 9)  /* data error checking - 0=disabled, 1=ECC check enable / gen disabled, 2=ECC check/gen enabled */
-#define ELBC_BR_WP        (1 << 8)            /* write protect */
-#define ELBC_BR_MSEL(n)   (((n) & 0x7) << 5)  /* machine select:
+#define ELBC_BR_ADDR(n)   (((uint32_t)n) & 0xFFFF8000UL) /* Physical base address - upper 17-bits */
+#define ELBC_BR_PS(n)     (((n) & 0x3UL) << 11) /* port size - 1=8-bit, 2=16-bit */
+#define ELBC_BR_DECC(n)   (((n) & 0x3UL) << 9)  /* data error checking - 0=disabled, 1=ECC check enable / gen disabled, 2=ECC check/gen enabled */
+#define ELBC_BR_WP        (1UL << 8)            /* write protect */
+#define ELBC_BR_MSEL(n)   (((n) & 0x7UL) << 5)  /* machine select:
                                                *   0=GPCM (General Purpose Chip-Select Machine)
                                                *   1=FCM (Flash Control Machine),
                                                *   4=UPMA, 5=UPMB, 6=UPMC (User Programmable Machines) */
-#define ELBC_BR_V         (1 << 0)            /* bank valid */
+#define ELBC_BR_V         (1UL << 0)            /* bank valid */
 
 /* eLBC OR */
 #define ELBC_OR_AMASK(n)  (((uint32_t)n) & 0xFFFF8000) /* Address mask - upper 17-bits */
 
 /* eLBC OR (FCM) */
-#define ELBC_ORF_BCTLD    (1 << 12) /* buffer control disable */
-#define ELBC_ORF_PGS      (1 << 10) /* page size 0=512, 1=2048 bytes */
-#define ELBC_ORF_CSCT     (1 << 9)  /* chip select to command time - TRLX=0 (0=1, 1=4), TRLX=1 (0=2, 1=8) clock cycles */
-#define ELBC_ORF_CST      (1 << 8)  /* command setup time - TRLX=0 (0=0 or 1=0.25) TRLX=1 (0=0.5 or 1=1) clock cycles */
-#define ELBC_ORF_CHT      (1 << 7)  /* command hold time - TRLX=0 (0=0.5 or 1=1) TRLX=1 (0=1.5 or 1=2) clock cycles */
-#define ELBC_ORF_SCY(n)   (((n) & 0x7) << 4) /* cycle length in bus clocks (0-7 bus clock cycle wait states) */
-#define ELBC_ORF_RST      (1 << 3)  /* read time setup - read enable asserted 1 clock */
-#define ELBC_ORF_TRLX     (1 << 2)  /* timing related */
-#define ELBC_ORF_EHTR     (1 << 1)  /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */
+#define ELBC_ORF_BCTLD    (1UL << 12) /* buffer control disable */
+#define ELBC_ORF_PGS      (1UL << 10) /* page size 0=512, 1=2048 bytes */
+#define ELBC_ORF_CSCT     (1UL << 9)  /* chip select to command time - TRLX=0 (0=1, 1=4), TRLX=1 (0=2, 1=8) clock cycles */
+#define ELBC_ORF_CST      (1UL << 8)  /* command setup time - TRLX=0 (0=0 or 1=0.25) TRLX=1 (0=0.5 or 1=1) clock cycles */
+#define ELBC_ORF_CHT      (1UL << 7)  /* command hold time - TRLX=0 (0=0.5 or 1=1) TRLX=1 (0=1.5 or 1=2) clock cycles */
+#define ELBC_ORF_SCY(n)   (((n) & 0x7UL) << 4) /* cycle length in bus clocks (0-7 bus clock cycle wait states) */
+#define ELBC_ORF_RST      (1UL << 3)  /* read time setup - read enable asserted 1 clock */
+#define ELBC_ORF_TRLX     (1UL << 2)  /* timing related */
+#define ELBC_ORF_EHTR     (1UL << 1)  /* extended hold time - LRLX=0 (0=1 or 1=2), LRLX=1 (0=2 or 1=8) inserted idle clock cycles */
 
 /* eLBC OR (GPCM) */
-#define ELBC_ORG_CSCT (1 << 11)
-#define ELBC_ORG_XACS (1 << 8)
-#define ELBC_ORG_SCY  (1 << 4)
-#define ELBC_ORG_TRLX (1 << 2)
-#define ELBC_ORG_EHTR (1 << 1)
-#define ELBC_ORG_EAD  (1 << 0)
+#define ELBC_ORG_CSCT (1UL << 11)
+#define ELBC_ORG_XACS (1UL << 8)
+#define ELBC_ORG_SCY  (1UL << 4)
+#define ELBC_ORG_TRLX (1UL << 2)
+#define ELBC_ORG_EHTR (1UL << 1)
+#define ELBC_ORG_EAD  (1UL << 0)
 
 
-#define ELBC_LSOR_BANK(n) ((n) & (ELBC_MAX_BANKS-1)) /* flash bank 0-7 */
+#define ELBC_LSOR_BANK(n) ((n) & (ELBC_MAX_BANKS-1UL)) /* flash bank 0-7 */
 
 #define ELBC_LBCR_ABSWP    (1 << 19)    /* Address byte swap for 16-bit port size */
 #define ELBC_LBCR_BMTPS(n) ((n) & 0xF) /* Bus monitor timer prescale */
 
 #define ELBC_FMR_CWTO(n)  (((n) & 0xF) << 12) /* command wait timeout 0=256 cycles, 15=8,388,608 cycles of LCLK */
 #define ELBC_FMR_BOOT     (1 << 11) /* flash auto-boot lead mode 0=FCM is op normal, 1=eLBC autoload 4-Kbyte boot block */
 #define ELBC_FMR_ECCM     (1 << 8)  /* ECC mode 0=ECC is checked/calc 6/8 spare, 1=8/10 spare */
-#define ELBC_FMR_AL(n)    (((n) & 0x3) << 4) /* address length 0=2 bytes, 1=3 bytes, 2=4 bytes issued for page address */
-#define ELBC_FMR_OP(n)    (((n) & 0x3) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */
+#define ELBC_FMR_AL(n)    (((n) & 0x3UL) << 4) /* address length 0=2 bytes, 1=3 bytes, 2=4 bytes issued for page address */
+#define ELBC_FMR_OP(n)    (((n) & 0x3UL) << 0) /* flash operation 0=normal, 1=sim auto-boot block load, 2=exe FIR cmd w/write protect enable, 3=exe FIR cmd */
 
-#define ELBC_FIR_OP(s,op) ((op) & 0xF) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */
+#define ELBC_FIR_OP(s,op) ((op) & 0xFUL) << (28 - ((s % 8) * 4)) /* up to 8 sequences of instructions */
 #define ELBC_FIR_OP_NOP 0  /* No-operation and end of operation sequence */
 #define ELBC_FIR_OP_CA  1  /* Issue current column address as set in FPAR, with length set by ORx[PGS] */
 #define ELBC_FIR_OP_PA  2  /* Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL] */
@@ -277,7 +277,7 @@ static int test_tpm(void);
 #define ELBC_FIR_OP_CW1 13 /* Wait for LFRB to return high or time-out, then issue command from FCR[CMD1] */
 #define ELBC_FIR_OP_RBW 14 /* Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device into current FCM RAM buffer */
 #define ELBC_FIR_OP_RSW 15 /* Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash device into next AS field of MDR */
-#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFF) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */
+#define ELBC_FCR_CMD(s,cmd) (((cmd) & 0xFFUL) << (24 - ((s % 4) * 8))) /* up to 4 command opcodes */
 
 #define ELBC_LCRR_CLKDIV_MASK 0x0000001F
 #define ELBC_LCRR_CLKDIV_4  0x2

hal/nxp_ppc.h

@@ -28,22 +28,22 @@
     #define CORE_E500
     #define LAW_MAX_ENTRIES 12
 
-    #define CCSRBAR_DEF (0xFF700000) /* P1021RM 4.3 default base */
+    #define CCSRBAR_DEF (0xFF700000UL) /* P1021RM 4.3 default base */
     #define CCSRBAR_SIZE BOOKE_PAGESZ_1M
 
     #define ENABLE_DDR
-    #define DDR_SIZE (512 * 1024 * 1024)
+    #define DDR_SIZE (512UL * 1024UL * 1024UL)
 
     /* Memory used for transferring blocks to/from NAND.
      * Maps to eLBC FCM internal 8KB region (by hardware) */
-    #define FLASH_BASE_ADDR 0xFC000000
+    #define FLASH_BASE_ADDR 0xFC000000UL
 
     #ifdef BUILD_LOADER_STAGE1
         /* First stage loader features */
 
         #define ENABLE_L2_CACHE
-        #define L2SRAM_ADDR   (0xF8F80000) /* L2 as SRAM */
-        #define L2SRAM_SIZE   (256 * 1024)
+        #define L2SRAM_ADDR   (0xF8F80000UL) /* L2 as SRAM */
+        #define L2SRAM_SIZE   (256UL * 1024UL)
 
         #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
         #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_256KB
@@ -55,7 +55,7 @@
         #define ENABLE_L2_CACHE
 
         /* Relocate CCSRBAR */
-        #define CCSRBAR 0xFFE00000
+        #define CCSRBAR 0xFFE00000UL
 
         #define ENABLE_INTERRUPTS
     #endif
@@ -88,7 +88,7 @@
     #define ENABLE_DDR
     #define DDR_SIZE (2048ULL * 1024ULL * 1024ULL)
 
-    #define FLASH_BASE_ADDR      0xEC000000
+    #define FLASH_BASE_ADDR      0xEC000000UL
     #define FLASH_BASE_PHYS_HIGH 0xFULL
     #define FLASH_LAW_SIZE       LAW_SIZE_64MB
     #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_64M
@@ -101,7 +101,7 @@
     #define CORE_E6500
     #define LAW_MAX_ENTRIES 32
 
-    #define CCSRBAR_DEF (0xFE000000) /* T2080RM 4.3.1 default base */
+    #define CCSRBAR_DEF (0xFE000000UL) /* T2080RM 4.3.1 default base */
     #define CCSRBAR_SIZE BOOKE_PAGESZ_16M
 
     /* relocate to 64-bit 0xE_ */
@@ -111,8 +111,8 @@
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
 
-    #define L2SRAM_ADDR   (0xF8F80000) /* L2 as SRAM */
-    #define L2SRAM_SIZE   (256 * 1024)
+    #define L2SRAM_ADDR   (0xF8F80000UL) /* L2 as SRAM */
+    #define L2SRAM_SIZE   (256UL * 1024UL)
 
     #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
     #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_256KB
@@ -122,9 +122,9 @@
     #define ENABLE_INTERRUPTS
 
     #define ENABLE_DDR
-    #define DDR_SIZE (8192 * 1024 * 1024)
+    #define DDR_SIZE (8192UL * 1024UL * 1024UL)
 
-    #define FLASH_BASE_ADDR      0xE8000000
+    #define FLASH_BASE_ADDR      0xE8000000UL
     #define FLASH_BASE_PHYS_HIGH 0x0ULL
     #define FLASH_LAW_SIZE       LAW_SIZE_128MB
     #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_128M
@@ -138,18 +138,18 @@
 
 /* boot address */
 #ifndef BOOT_ROM_ADDR
-#define BOOT_ROM_ADDR 0xFFFFF000
+#define BOOT_ROM_ADDR 0xFFFFF000UL
 #endif
 #ifndef BOOT_ROM_SIZE
-#define BOOT_ROM_SIZE (4*1024)
+#define BOOT_ROM_SIZE (4UL*1024UL)
 #endif
 
 /* reset vector */
 #define RESET_VECTOR (BOOT_ROM_ADDR + (BOOT_ROM_SIZE - 4))
 
 /* CCSRBAR */
 #ifndef CCSRBAR_DEF
-#define CCSRBAR_DEF  0xFE000000
+#define CCSRBAR_DEF  0xFE000000UL
 #endif
 #ifndef CCSRBAR
 #define CCSRBAR      CCSRBAR_DEF
@@ -163,7 +163,7 @@
 
 /* DDR */
 #ifndef DDR_ADDRESS
-#define DDR_ADDRESS  0x00000000
+#define DDR_ADDRESS  0x00000000UL
 #endif
 
 /* L1 */

hal/skeleton.c

@@ -40,6 +40,7 @@ void hal_prepare_boot(void)
 
 int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
 {
+    return 0; /* on success. */
 }
 
 void RAMFUNCTION hal_flash_unlock(void)
@@ -52,5 +53,6 @@ void RAMFUNCTION hal_flash_lock(void)
 
 int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 {
+    return 0; /* on success. */
 }
 

hal/stm32f4.c

@@ -84,7 +84,7 @@
 #define FLASH_SR_OPERR                        (1 << 1)
 #define FLASH_SR_EOP                          (1 << 0)
 
-#define FLASH_CR_LOCK               (uint32_t)(1 << 31)
+#define FLASH_CR_LOCK                         (1UL << 31)
 #define FLASH_CR_ERRIE                        (1 << 25)
 #define FLASH_CR_EOPIE                        (1 << 24)
 #define FLASH_CR_STRT                         (1 << 16)

hal/stm32f7.c

@@ -86,7 +86,7 @@
 #define FLASH_SR_OPERR                        (1 << 1)
 #define FLASH_SR_EOP                          (1 << 0)
 
-#define FLASH_CR_LOCK                         (1 << 31)
+#define FLASH_CR_LOCK                         (1UL << 31)
 #define FLASH_CR_ERRIE                        (1 << 25)
 #define FLASH_CR_EOPIE                        (1 << 24)
 #define FLASH_CR_STRT                         (1 << 16)

hal/stm32g0.c

@@ -80,7 +80,7 @@
 #define FLASH_SR_PROGERR                      (1 << 3)
 #define FLASH_SR_EOP                          (1 << 0)  /* RM0444 - 3.7.4 - FLASH_SR */
 
-#define FLASH_CR_LOCK                         (1 << 31) /* RM0444 - 3.7.5 - FLASH_CR */
+#define FLASH_CR_LOCK                         (1UL << 31) /* RM0444 - 3.7.5 - FLASH_CR */
 #define FLASH_CR_STRT                         (1 << 16) /* RM0444 - 3.7.5 - FLASH_CR */
 
 #define FLASH_CR_PER                          (1 << 1)  /* RM0444 - 3.7.5 - FLASH_CR */

hal/stm32l5_ns.c

@@ -165,7 +165,7 @@
 #define FLASH_CR_ERRIE                      (1 << 25)
 #define FLASH_CR_OBL_LAUNCH                 (1 << 27)
 #define FLASH_CR_OPTLOCK                    (1 << 30)
-#define FLASH_CR_LOCK                       (1 << 31)
+#define FLASH_CR_LOCK                       (1UL << 31)
 
 #define FLASH_ACR           (*(volatile uint32_t *)(FLASH_BASE + 0x00))
 #define FLASH_ACR_LATENCY_MASK              (0x0F)

hal/stm32u5.c

@@ -177,7 +177,7 @@ int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
 {
     uint32_t end_address;
     uint32_t p;
-    volatile uint32_t *cr;
+    volatile uint32_t *cr = &FLASH_NS_CR;
 
     flash_clear_errors(0);
     if (len == 0)